From 75e4e7c9bc436681711290f331021faa33cd04b7 Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Mon, 28 Jan 2019 16:39:25 -0500 Subject: [PATCH] gpu: nvgpu: clk: address MISRA 10.3 violations This fixes a number of miscellaneous MISRA 10.3 violations in common/pmu/clk/ for assignment of objects of different size or essential type. JIRA NVGPU-1008 Change-Id: If93aa9fc4f0f49ea678e39111f323ef4d53f5ec5 Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/2008771 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/pmu/clk/clk.c | 2 +- drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c | 10 +++++----- drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h | 4 ++-- .../gpu/nvgpu/common/pmu/clk/clk_freq_controller.c | 4 ++-- drivers/gpu/nvgpu/common/pmu/clk/clk_freq_domain.c | 11 ++++++++--- drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c | 12 ++++++------ drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c | 10 +++++----- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/pmu.h | 2 +- 9 files changed, 31 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk.c b/drivers/gpu/nvgpu/common/pmu/clk/clk.c index 2b1a332cf..3cee9386f 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk.c @@ -1024,7 +1024,7 @@ int nvgpu_clk_set_boot_fll_clk_tu10x(struct gk20a *g) } change_input.pstate_index = 0U; - change_input.flags = CTRL_PERF_CHANGE_SEQ_CHANGE_FORCE; + change_input.flags = (u32)CTRL_PERF_CHANGE_SEQ_CHANGE_FORCE; change_input.vf_points_cache_counter = 0xFFFFFFFFU; status = clk_domain_freq_to_volt(g, gpcclk_domain, diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c index 3ab98917f..0f3d839c4 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -297,7 +297,7 @@ static int devinit_get_fll_device_table(struct gk20a *g, if (pvin_dev == NULL) { return -EINVAL; } else { - pvin_dev->flls_shared_mask |= BIT(fll_id); + pvin_dev->flls_shared_mask |= BIT32(fll_id); } } else { /* Return if Logic ADC device index is invalid*/ @@ -315,7 +315,7 @@ static int devinit_get_fll_device_table(struct gk20a *g, if (pvin_dev == NULL) { return -EINVAL; } else { - pvin_dev->flls_shared_mask |= BIT(fll_id); + pvin_dev->flls_shared_mask |= BIT32(fll_id); } } else { /* Make sure VSELECT mode is set correctly to _LOGIC*/ @@ -406,7 +406,7 @@ u32 nvgpu_clk_get_vbios_clk_domain_gp10x( u32 vbios_domain) return 0; } -static u32 lutbroadcastslaveregister(struct gk20a *g, +static int lutbroadcastslaveregister(struct gk20a *g, struct avfsfllobjs *pfllobjs, struct fll_device *pfll, struct fll_device *pfll_slave) @@ -430,7 +430,7 @@ static struct fll_device *construct_fll_device(struct gk20a *g, nvgpu_log_info(g, " "); status = boardobj_construct_super(g, &board_obj_ptr, - sizeof(struct fll_device), pargs); + (u32)sizeof(struct fll_device), pargs); if (status != 0) { return NULL; } diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h index 19559e45d..2576eca76 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -30,7 +30,7 @@ struct fll_device; struct avfsfllobjs; -typedef u32 fll_lut_broadcast_slave_register(struct gk20a *g, +typedef int fll_lut_broadcast_slave_register(struct gk20a *g, struct avfsfllobjs *pfllobjs, struct fll_device *pfll, struct fll_device *pfll_slave); diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c index a448e5eb5..3fc6a4fe5 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -169,7 +169,7 @@ static struct clk_freq_controller *clk_clk_freq_controller_construct( } status = clk_freq_controller_construct_pi(g, &board_obj_ptr, - sizeof(struct clk_freq_controller_pi), pargs); + (u16)sizeof(struct clk_freq_controller_pi), pargs); if (status != 0) { return NULL; } diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_domain.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_domain.c index f8625209d..5e2e55e06 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_domain.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_domain.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,7 @@ #include #include #include +#include #include "clk.h" #include "clk_freq_domain.h" @@ -139,8 +140,9 @@ int nvgpu_clk_freq_domain_sw_setup(struct gk20a *g) struct boardobj *pboardobj = NULL; struct nvgpu_clk_freq_domain *pfreq_domain = NULL; struct nvgpu_clk_freq_domain_grp *pfreq_domain_grp = NULL; - u8 num_of_domains = sizeof(clk_freq_domain_type) / + size_t tmp_num_of_domains = sizeof(clk_freq_domain_type) / sizeof(struct domain_type); + u8 num_of_domains; int status = 0; u8 idx = 0; @@ -149,6 +151,9 @@ int nvgpu_clk_freq_domain_sw_setup(struct gk20a *g) struct nvgpu_clk_freq_domain freq_domain; }freq_domain_data; + nvgpu_assert(tmp_num_of_domains <= U8_MAX); + num_of_domains = (u8)tmp_num_of_domains; + pboardobjgrp = &g->clk_pmu->freq_domain_grp_objs.super.super; pfreq_domain_grp = &g->clk_pmu->freq_domain_grp_objs; @@ -189,7 +194,7 @@ int nvgpu_clk_freq_domain_sw_setup(struct gk20a *g) pboardobj = NULL; status = boardobj_construct_super(g,&pboardobj, - sizeof(struct nvgpu_clk_freq_domain), + (u16)sizeof(struct nvgpu_clk_freq_domain), (void*)&freq_domain_data); if(status != 0) { nvgpu_err(g, "Failed to construct nvgpu_clk_freq_domain Board obj"); diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c index 27b504888..8c639d08c 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c @@ -282,7 +282,7 @@ static int clk_vf_point_construct_volt(struct gk20a *g, return -EINVAL; } - ptmpobj->type_mask = BIT(CTRL_CLK_CLK_VF_POINT_TYPE_VOLT); + ptmpobj->type_mask = BIT32(CTRL_CLK_CLK_VF_POINT_TYPE_VOLT); status = clk_vf_point_construct_super(g, ppboardobj, size, pargs); if (status != 0) { return -EINVAL; @@ -313,7 +313,7 @@ static int clk_vf_point_construct_freq(struct gk20a *g, return -EINVAL; } - ptmpobj->type_mask = BIT(CTRL_CLK_CLK_VF_POINT_TYPE_FREQ); + ptmpobj->type_mask = BIT32(CTRL_CLK_CLK_VF_POINT_TYPE_FREQ); status = clk_vf_point_construct_super(g, ppboardobj, size, pargs); if (status != 0) { return -EINVAL; @@ -401,22 +401,22 @@ struct clk_vf_point *construct_clk_vf_point(struct gk20a *g, void *pargs) switch (BOARDOBJ_GET_TYPE(pargs)) { case CTRL_CLK_CLK_VF_POINT_TYPE_FREQ: status = clk_vf_point_construct_freq(g, &board_obj_ptr, - sizeof(struct clk_vf_point_freq), pargs); + (u16)sizeof(struct clk_vf_point_freq), pargs); break; case CTRL_CLK_CLK_VF_POINT_TYPE_VOLT: status = clk_vf_point_construct_volt(g, &board_obj_ptr, - sizeof(struct clk_vf_point_volt), pargs); + (u16)sizeof(struct clk_vf_point_volt), pargs); break; case CTRL_CLK_CLK_VF_POINT_TYPE_35_FREQ: status = clk_vf_point_construct_freq_35(g, &board_obj_ptr, - sizeof(struct clk_vf_point_freq), pargs); + (u16)sizeof(struct clk_vf_point_freq), pargs); break; case CTRL_CLK_CLK_VF_POINT_TYPE_35_VOLT: status = clk_vf_point_construct_volt_35(g, &board_obj_ptr, - sizeof(struct clk_vf_point_volt), pargs); + (u16)sizeof(struct clk_vf_point_volt), pargs); break; default: diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c index bf6b2c80e..9961db23d 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -386,7 +386,7 @@ static int vin_device_construct_v10(struct gk20a *g, return -EINVAL; } - ptmpobj->type_mask |= BIT(CTRL_CLK_VIN_TYPE_V10); + ptmpobj->type_mask |= BIT32(CTRL_CLK_VIN_TYPE_V10); status = vin_device_construct_super(g, ppboardobj, size, pargs); if (status != 0) { return -EINVAL; @@ -416,7 +416,7 @@ static int vin_device_construct_v20(struct gk20a *g, return -EINVAL; } - ptmpobj->type_mask |= BIT(CTRL_CLK_VIN_TYPE_V20); + ptmpobj->type_mask |= BIT32(CTRL_CLK_VIN_TYPE_V20); status = vin_device_construct_super(g, ppboardobj, size, pargs); if (status != 0) { return -EINVAL; @@ -468,12 +468,12 @@ static struct vin_device *construct_vin_device(struct gk20a *g, void *pargs) switch (BOARDOBJ_GET_TYPE(pargs)) { case CTRL_CLK_VIN_TYPE_V10: status = vin_device_construct_v10(g, &board_obj_ptr, - sizeof(struct vin_device_v10), pargs); + (u16)sizeof(struct vin_device_v10), pargs); break; case CTRL_CLK_VIN_TYPE_V20: status = vin_device_construct_v20(g, &board_obj_ptr, - sizeof(struct vin_device_v20), pargs); + (u16)sizeof(struct vin_device_v20), pargs); break; default: diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 725390fbe..4169ee0eb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -1268,7 +1268,7 @@ struct gpu_ops { int (*perf_pmu_vfe_load)(struct gk20a *g); bool support_clk_freq_domain; bool support_vf_point; - u32 lut_num_entries; + u8 lut_num_entries; } clk; struct { int (*arbiter_clk_init)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index 7828bcc98..a5af1e2d9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h @@ -169,7 +169,7 @@ enum pmu_seq_state { (_prpc)->hdr.flags = 0x0; \ \ _stat = nvgpu_pmu_rpc_execute(_pmu, &((_prpc)->hdr), \ - (sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\ + (u16)(sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\ (_size), NULL, NULL, true); \ } while (false)