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gpu: nvgpu: drop user callback support in CE
Simplify the copyengine code by deleting support for the ce_event_callback feature that has never been used. Similarly, create a channel without the finish callback to get rid of that Linux dependency, and delete the finish callback function as it now serves no purpose. Delete also the submitted_seq_number and completed_seq_number fields that are only written to. Jira NVGPU-259 Change-Id: I02d15bdcb546f4dd8895a6bfb5130caf88a104e2 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1589320 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -173,7 +173,6 @@ int gk20a_ce_execute_ops(struct gk20a *g,
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/* Next available command buffer queue Index */
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/* Next available command buffer queue Index */
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++ce_ctx->cmd_buf_read_queue_offset;
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++ce_ctx->cmd_buf_read_queue_offset;
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++ce_ctx->submitted_seq_number;
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}
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}
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} else {
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} else {
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ret = -ENOMEM;
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ret = -ENOMEM;
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@@ -259,12 +259,11 @@ void nvgpu_init_mm_ce_context(struct gk20a *g)
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#if defined(CONFIG_GK20A_VIDMEM)
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#if defined(CONFIG_GK20A_VIDMEM)
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if (g->mm.vidmem.size && (g->mm.vidmem.ce_ctx_id == (u32)~0)) {
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if (g->mm.vidmem.size && (g->mm.vidmem.ce_ctx_id == (u32)~0)) {
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g->mm.vidmem.ce_ctx_id =
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g->mm.vidmem.ce_ctx_id =
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gk20a_ce_create_context_with_cb(g,
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gk20a_ce_create_context(g,
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gk20a_fifo_get_fast_ce_runlist_id(g),
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gk20a_fifo_get_fast_ce_runlist_id(g),
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-1,
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-1,
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-1,
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-1,
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-1,
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-1);
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NULL);
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if (g->mm.vidmem.ce_ctx_id == (u32)~0)
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if (g->mm.vidmem.ce_ctx_id == (u32)~0)
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nvgpu_err(g,
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nvgpu_err(g,
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@@ -103,54 +103,6 @@ int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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}
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}
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/* static CE app api */
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/* static CE app api */
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static void gk20a_ce_notify_all_user(struct gk20a *g, u32 event)
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{
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struct gk20a_ce_app *ce_app = &g->ce_app;
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struct gk20a_gpu_ctx *ce_ctx, *ce_ctx_save;
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if (!ce_app->initialised)
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return;
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nvgpu_mutex_acquire(&ce_app->app_mutex);
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nvgpu_list_for_each_entry_safe(ce_ctx, ce_ctx_save,
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&ce_app->allocated_contexts, gk20a_gpu_ctx, list) {
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if (ce_ctx->user_event_callback) {
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ce_ctx->user_event_callback(ce_ctx->ctx_id,
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event);
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}
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}
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nvgpu_mutex_release(&ce_app->app_mutex);
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}
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static void gk20a_ce_finished_ctx_cb(struct channel_gk20a *ch, void *data)
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{
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struct gk20a_gpu_ctx *ce_ctx = data;
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bool channel_idle;
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u32 event;
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channel_gk20a_joblist_lock(ch);
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channel_idle = channel_gk20a_joblist_is_empty(ch);
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channel_gk20a_joblist_unlock(ch);
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if (!channel_idle)
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return;
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gk20a_dbg(gpu_dbg_fn, "ce: finished %p", ce_ctx);
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if (ch->has_timedout)
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event = NVGPU_CE_CONTEXT_JOB_TIMEDOUT;
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else
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event = NVGPU_CE_CONTEXT_JOB_COMPLETED;
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if (ce_ctx->user_event_callback)
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ce_ctx->user_event_callback(ce_ctx->ctx_id,
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event);
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++ce_ctx->completed_seq_number;
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}
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static void gk20a_ce_free_command_buffer_stored_fence(struct gk20a_gpu_ctx *ce_ctx)
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static void gk20a_ce_free_command_buffer_stored_fence(struct gk20a_gpu_ctx *ce_ctx)
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{
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{
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u32 cmd_buf_index;
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u32 cmd_buf_index;
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@@ -410,7 +362,6 @@ int gk20a_init_ce_support(struct gk20a *g)
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if (ce_app->initialised) {
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if (ce_app->initialised) {
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/* assume this happen during poweron/poweroff GPU sequence */
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/* assume this happen during poweron/poweroff GPU sequence */
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ce_app->app_state = NVGPU_CE_ACTIVE;
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ce_app->app_state = NVGPU_CE_ACTIVE;
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gk20a_ce_notify_all_user(g, NVGPU_CE_CONTEXT_RESUME);
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return 0;
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return 0;
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}
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}
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@@ -469,18 +420,16 @@ void gk20a_ce_suspend(struct gk20a *g)
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return;
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return;
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ce_app->app_state = NVGPU_CE_SUSPEND;
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ce_app->app_state = NVGPU_CE_SUSPEND;
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gk20a_ce_notify_all_user(g, NVGPU_CE_CONTEXT_SUSPEND);
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return;
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return;
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}
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}
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/* CE app utility functions */
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/* CE app utility functions */
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u32 gk20a_ce_create_context_with_cb(struct gk20a *g,
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u32 gk20a_ce_create_context(struct gk20a *g,
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int runlist_id,
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int runlist_id,
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int priority,
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int priority,
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int timeslice,
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int timeslice,
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int runlist_level,
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int runlist_level)
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ce_event_callback user_event_callback)
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{
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{
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struct gk20a_gpu_ctx *ce_ctx;
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struct gk20a_gpu_ctx *ce_ctx;
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struct gk20a_ce_app *ce_app = &g->ce_app;
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struct gk20a_ce_app *ce_app = &g->ce_app;
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@@ -501,15 +450,11 @@ u32 gk20a_ce_create_context_with_cb(struct gk20a *g,
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}
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}
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ce_ctx->g = g;
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ce_ctx->g = g;
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ce_ctx->user_event_callback = user_event_callback;
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ce_ctx->cmd_buf_read_queue_offset = 0;
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ce_ctx->cmd_buf_read_queue_offset = 0;
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ce_ctx->cmd_buf_end_queue_offset =
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ce_ctx->cmd_buf_end_queue_offset =
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(NVGPU_CE_COMMAND_BUF_SIZE / NVGPU_CE_MAX_COMMAND_BUFF_SIZE_PER_KICKOFF);
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(NVGPU_CE_COMMAND_BUF_SIZE / NVGPU_CE_MAX_COMMAND_BUFF_SIZE_PER_KICKOFF);
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ce_ctx->submitted_seq_number = 0;
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ce_ctx->completed_seq_number = 0;
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ce_ctx->vm = g->mm.ce.vm;
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ce_ctx->vm = g->mm.ce.vm;
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if (nvgpu_is_enabled(g, NVGPU_MM_CE_TSG_REQUIRED)) {
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if (nvgpu_is_enabled(g, NVGPU_MM_CE_TSG_REQUIRED)) {
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@@ -523,10 +468,7 @@ u32 gk20a_ce_create_context_with_cb(struct gk20a *g,
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}
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}
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/* always kernel client needs privileged channel */
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/* always kernel client needs privileged channel */
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ce_ctx->ch = gk20a_open_new_channel_with_cb(g, gk20a_ce_finished_ctx_cb,
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ce_ctx->ch = gk20a_open_new_channel(g, runlist_id, true);
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ce_ctx,
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runlist_id,
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true);
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if (!ce_ctx->ch) {
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if (!ce_ctx->ch) {
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nvgpu_err(g, "ce: gk20a channel not available");
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nvgpu_err(g, "ce: gk20a channel not available");
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goto end;
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goto end;
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@@ -613,7 +555,7 @@ end:
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return ctx_id;
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return ctx_id;
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}
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}
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EXPORT_SYMBOL(gk20a_ce_create_context_with_cb);
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EXPORT_SYMBOL(gk20a_ce_create_context);
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void gk20a_ce_delete_context(struct gk20a *g,
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void gk20a_ce_delete_context(struct gk20a *g,
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u32 ce_ctx_id)
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u32 ce_ctx_id)
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@@ -40,8 +40,6 @@ int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
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#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_PER_KICKOFF 256
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#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_PER_KICKOFF 256
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#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_FOR_TRACING 8
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#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_FOR_TRACING 8
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typedef void (*ce_event_callback)(u32 ce_ctx_id, u32 ce_event_flag);
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/* dma launch_flags */
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/* dma launch_flags */
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enum {
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enum {
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/* location */
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/* location */
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@@ -69,14 +67,6 @@ enum {
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NVGPU_CE_MEMSET = (1 << 1),
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NVGPU_CE_MEMSET = (1 << 1),
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};
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};
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/* CE event flags */
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enum {
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NVGPU_CE_CONTEXT_JOB_COMPLETED = (1 << 0),
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NVGPU_CE_CONTEXT_JOB_TIMEDOUT = (1 << 1),
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NVGPU_CE_CONTEXT_SUSPEND = (1 << 2),
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NVGPU_CE_CONTEXT_RESUME = (1 << 3),
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};
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/* CE app state machine flags */
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/* CE app state machine flags */
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enum {
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enum {
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NVGPU_CE_ACTIVE = (1 << 0),
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NVGPU_CE_ACTIVE = (1 << 0),
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@@ -106,7 +96,6 @@ struct gk20a_gpu_ctx {
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u32 ctx_id;
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u32 ctx_id;
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struct nvgpu_mutex gpu_ctx_mutex;
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struct nvgpu_mutex gpu_ctx_mutex;
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int gpu_ctx_state;
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int gpu_ctx_state;
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ce_event_callback user_event_callback;
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/* tsg related data */
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/* tsg related data */
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struct tsg_gk20a *tsg;
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struct tsg_gk20a *tsg;
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@@ -120,9 +109,6 @@ struct gk20a_gpu_ctx {
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struct nvgpu_list_node list;
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struct nvgpu_list_node list;
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u64 submitted_seq_number;
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u64 completed_seq_number;
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u32 cmd_buf_read_queue_offset;
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u32 cmd_buf_read_queue_offset;
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u32 cmd_buf_end_queue_offset;
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u32 cmd_buf_end_queue_offset;
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};
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};
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@@ -140,12 +126,11 @@ void gk20a_ce_suspend(struct gk20a *g);
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void gk20a_ce_destroy(struct gk20a *g);
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void gk20a_ce_destroy(struct gk20a *g);
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/* CE app utility functions */
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/* CE app utility functions */
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u32 gk20a_ce_create_context_with_cb(struct gk20a *g,
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u32 gk20a_ce_create_context(struct gk20a *g,
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int runlist_id,
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int runlist_id,
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int priority,
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int priority,
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int timeslice,
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int timeslice,
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int runlist_level,
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int runlist_level);
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ce_event_callback user_event_callback);
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int gk20a_ce_execute_ops(struct gk20a *g,
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int gk20a_ce_execute_ops(struct gk20a *g,
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u32 ce_ctx_id,
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u32 ce_ctx_id,
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u64 src_buf,
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u64 src_buf,
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