diff --git a/arch/nvgpu-hal-new.yaml b/arch/nvgpu-hal-new.yaml index 75852d9d3..be90adaa0 100644 --- a/arch/nvgpu-hal-new.yaml +++ b/arch/nvgpu-hal-new.yaml @@ -795,7 +795,9 @@ xve: gpu: dgpu sources: [ include/nvgpu/xve.h, hal/xve/xve_gp106.c, - hal/xve/xve_gp106.h ] + hal/xve/xve_gp106.h, + hal/xve/xve_tu104.c, + hal/xve/xve_tu104.h ] tpc: safe: no diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index db5c47009..251711504 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -312,7 +312,8 @@ nvgpu-y += \ hal/top/top_gp106.o \ hal/top/top_gv100.o \ hal/tpc/tpc_gv11b.o \ - hal/xve/xve_gp106.o + hal/xve/xve_gp106.o \ + hal/xve/xve_tu104.o # Linux specific parts of nvgpu. diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 8e58738bb..af2f4b6d6 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -634,7 +634,8 @@ srcs += common/sec2/sec2.c \ hal/pramin/pramin_tu104.c \ hal/bios/bios_tu104.c \ hal/top/top_gv100.c \ - hal/xve/xve_gp106.c + hal/xve/xve_gp106.c \ + hal/xve/xve_tu104.c ifeq ($(CONFIG_NVGPU_COMPRESSION),1) srcs += hal/cbc/cbc_tu104.c diff --git a/drivers/gpu/nvgpu/hal/clk/clk_tu104.c b/drivers/gpu/nvgpu/hal/clk/clk_tu104.c index bc8d22342..8656370e2 100644 --- a/drivers/gpu/nvgpu/hal/clk/clk_tu104.c +++ b/drivers/gpu/nvgpu/hal/clk/clk_tu104.c @@ -377,3 +377,9 @@ void tu104_get_change_seq_time(struct gk20a *g, s64 *change_time) *change_time = diff; } + +void tu104_change_host_clk_source(struct gk20a *g) +{ + nvgpu_writel(g, trim_sys_ind_clk_sys_core_clksrc_r(), + trim_sys_ind_clk_sys_core_clksrc_hostclk_fll_f()); +} diff --git a/drivers/gpu/nvgpu/hal/clk/clk_tu104.h b/drivers/gpu/nvgpu/hal/clk/clk_tu104.h index 4aa813040..d1050c682 100644 --- a/drivers/gpu/nvgpu/hal/clk/clk_tu104.h +++ b/drivers/gpu/nvgpu/hal/clk/clk_tu104.h @@ -37,4 +37,5 @@ int tu104_clk_domain_get_f_points( u16 *pfreqpointsinmhz); unsigned long tu104_clk_maxrate(struct gk20a *g, u32 api_domain); void tu104_get_change_seq_time(struct gk20a *g, s64 *change_time); +void tu104_change_host_clk_source(struct gk20a *g); #endif /* CLK_TU104_H */ diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 31d3c7d36..6ea530ae7 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -164,6 +164,7 @@ #include "hal/bios/bios_tu104.h" #include "hal/pramin/pramin_init.h" #include "hal/xve/xve_gp106.h" +#include "hal/xve/xve_tu104.h" #include "common/nvlink/init/device_reginit_gv100.h" #include "common/nvlink/intr_and_err_handling_gv100.h" @@ -1240,6 +1241,7 @@ static const struct gpu_ops tu104_ops = { .clk_domain_get_f_points = tu104_clk_domain_get_f_points, .get_maxrate = tu104_clk_maxrate, .get_change_seq_time = tu104_get_change_seq_time, + .change_host_clk_source = tu104_change_host_clk_source, }, #ifdef CONFIG_NVGPU_CLK_ARB .clk_arb = { @@ -1382,6 +1384,7 @@ static const struct gpu_ops tu104_ops = { #endif .enable_shadow_rom = NULL, .disable_shadow_rom = NULL, + .devinit_deferred_settings = tu104_devinit_deferred_settings, }, .falcon = { .falcon_sw_init = nvgpu_falcon_sw_init, @@ -1642,6 +1645,7 @@ int tu104_init_hal(struct gk20a *g) nvgpu_set_enabled(g, NVGPU_SUPPORT_PMU_SUPER_SURFACE, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_DGPU_THERMAL_ALERT, true); + nvgpu_set_enabled(g, NVGPU_SUPPORT_DGPU_PCIE_SCRIPT_EXECUTE, true); /* for now */ gops->clk.support_clk_freq_controller = false; diff --git a/drivers/gpu/nvgpu/hal/xve/xve_tu104.c b/drivers/gpu/nvgpu/hal/xve/xve_tu104.c new file mode 100644 index 000000000..edb3b9e51 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/xve/xve_tu104.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include + +#include "xve_tu104.h" +#include "xve_gp106.h" + +#include +#include + +#define DL_TIMER_LIMIT 0x58EU + +void tu104_devinit_deferred_settings(struct gk20a *g) +{ + u32 data; + g->ops.xve.xve_writel(g, xve_pcie_capability_r(), + xve_pcie_capability_gen2_capable_enable_f() | + xve_pcie_capability_gen3_capable_enable_f()); + nvgpu_writel(g, xp_dl_mgr_timing_r(0), DL_TIMER_LIMIT); + data = xve_high_latency_snoop_latency_value_init_f() | + xve_high_latency_snoop_latency_scale_init_f() | + xve_high_latency_no_snoop_latency_value_init_f() | + xve_high_latency_no_snoop_latency_scale_init_f(); + g->ops.xve.xve_writel(g, xve_high_latency_r(), data); + g->ops.xve.xve_writel(g, xve_ltr_msg_ctrl_r(), + xve_ltr_msg_ctrl_trigger_not_pending_f()); +} diff --git a/drivers/gpu/nvgpu/hal/xve/xve_tu104.h b/drivers/gpu/nvgpu/hal/xve/xve_tu104.h new file mode 100644 index 000000000..bac4bf184 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/xve/xve_tu104.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_XVE_TU104_H +#define NVGPU_XVE_TU104_H + +#ifdef CONFIG_NVGPU_DGPU +void tu104_devinit_deferred_settings(struct gk20a *g); +#endif + +#endif /* NVGPU_XVE_TU104_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index 941d4f4db..e191567e3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h @@ -237,10 +237,13 @@ struct gk20a; /** SW Quiesce */ #define NVGPU_DISABLE_SW_QUIESCE 81U -/** +/** DGPU PCIe Script Update */ +#define NVGPU_SUPPORT_DGPU_PCIE_SCRIPT_EXECUTE 82U + +/* * Must be greater than the largest bit offset in the above list. */ -#define NVGPU_MAX_ENABLED_BITS 82U +#define NVGPU_MAX_ENABLED_BITS 83U /** * @brief Check if the passed flag is enabled. diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 707ab89d6..96bc1d818 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -435,6 +435,7 @@ struct gpu_ops { void (*mclk_deinit)(struct gk20a *g); int (*mclk_change)(struct gk20a *g, u16 val); void (*get_change_seq_time)(struct gk20a *g, s64 *change_time); + void (*change_host_clk_source)(struct gk20a *g); bool split_rail_support; bool support_clk_freq_controller; bool support_pmgr_domain; @@ -578,6 +579,7 @@ struct gpu_ops { void (*enable_shadow_rom)(struct gk20a *g); void (*disable_shadow_rom)(struct gk20a *g); u32 (*get_link_control_status)(struct gk20a *g); + void (*devinit_deferred_settings)(struct gk20a *g); } xve; #endif struct gops_falcon falcon; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_trim_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_trim_tu104.h index b098ec1af..a7981dc3c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_trim_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_trim_tu104.h @@ -137,4 +137,6 @@ #define trim_sys_fr_clk_cntr_sysclk_cfg_source_sys_noeg_f() (0x0U) #define trim_sys_fr_clk_cntr_sysclk_cntr0_r() (0x00137630U) #define trim_sys_fr_clk_cntr_sysclk_cntr1_r() (0x00137634U) +#define trim_sys_ind_clk_sys_core_clksrc_r() (0x00137c00U) +#define trim_sys_ind_clk_sys_core_clksrc_hostclk_fll_f() (0x180U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xp_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xp_tu104.h index 65a1b14d8..68c193b69 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xp_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xp_tu104.h @@ -82,4 +82,6 @@ #define xp_pl_link_config_target_tx_width_x4_v() (0x00000005U) #define xp_pl_link_config_target_tx_width_x8_v() (0x00000004U) #define xp_pl_link_config_target_tx_width_x16_v() (0x00000000U) +#define xp_dl_mgr_timing_r(i)\ + (nvgpu_safe_add_u32(0x0008b400U, nvgpu_safe_mult_u32((i), 4U))) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xve_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xve_tu104.h index 327f58fbe..decbaa9c6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xve_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xve_tu104.h @@ -96,4 +96,14 @@ #define xve_reset_clock_counter_val_f(v) ((U32(v) & 0x7ffU) << 17U) #define xve_reset_clock_counter_val_m() (U32(0x7ffU) << 17U) #define xve_reset_clock_counter_val_v(r) (((r) >> 17U) & 0x7ffU) +#define xve_pcie_capability_r() (0x00000610U) +#define xve_pcie_capability_gen2_capable_enable_f() (0x1U) +#define xve_pcie_capability_gen3_capable_enable_f() (0x1000U) +#define xve_high_latency_r() (0x00000a10U) +#define xve_high_latency_snoop_latency_value_init_f() (0xfaU) +#define xve_high_latency_snoop_latency_scale_init_f() (0x400U) +#define xve_high_latency_no_snoop_latency_value_init_f() (0xfa0000U) +#define xve_high_latency_no_snoop_latency_scale_init_f() (0x4000000U) +#define xve_ltr_msg_ctrl_r() (0x00000a20U) +#define xve_ltr_msg_ctrl_trigger_not_pending_f() (0x0U) #endif diff --git a/drivers/gpu/nvgpu/os/linux/module.c b/drivers/gpu/nvgpu/os/linux/module.c index 2f612016a..5632d6e77 100644 --- a/drivers/gpu/nvgpu/os/linux/module.c +++ b/drivers/gpu/nvgpu/os/linux/module.c @@ -441,6 +441,12 @@ int gk20a_pm_finalize_poweron(struct device *dev) g->sim->sim_init_late(g); } + if (nvgpu_is_enabled(g, NVGPU_SUPPORT_DGPU_PCIE_SCRIPT_EXECUTE) && + nvgpu_platform_is_silicon(g)) { + g->ops.clk.change_host_clk_source(g); + g->ops.xve.devinit_deferred_settings(g); + } + if (nvgpu_is_enabled(g, NVGPU_SUPPORT_DGPU_THERMAL_ALERT) && nvgpu_platform_is_silicon(g)) { err = nvgpu_request_therm_irq(l);