From 76adb91f60f673ad8d6d797a9159aa6e7828b356 Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Tue, 3 Dec 2019 15:42:27 -0500 Subject: [PATCH] gpu: nvgpu: unit: add CE unit test Add unit test for the common.ce unit and the gv11b CE FUSA HALs. JIRA NVGPU-930 Change-Id: Idee75a1a5b53d397047edbead0db68ae999ce640 Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/2255473 Reviewed-by: mobile promotions Tested-by: mobile promotions --- Makefile.umbrella.tmk | 1 + drivers/gpu/nvgpu/libnvgpu-drv_safe.export | 6 + userspace/Makefile.sources | 1 + userspace/required_tests.json | 48 +++ userspace/units/ce/Makefile | 26 ++ userspace/units/ce/Makefile.interface.tmk | 23 ++ userspace/units/ce/Makefile.tmk | 24 ++ userspace/units/ce/nvgpu-ce.c | 363 +++++++++++++++++++++ userspace/units/ce/nvgpu-ce.h | 211 ++++++++++++ 9 files changed, 703 insertions(+) create mode 100644 userspace/units/ce/Makefile create mode 100644 userspace/units/ce/Makefile.interface.tmk create mode 100644 userspace/units/ce/Makefile.tmk create mode 100644 userspace/units/ce/nvgpu-ce.c create mode 100644 userspace/units/ce/nvgpu-ce.h diff --git a/Makefile.umbrella.tmk b/Makefile.umbrella.tmk index 30ec69c80..737ebc262 100644 --- a/Makefile.umbrella.tmk +++ b/Makefile.umbrella.tmk @@ -107,6 +107,7 @@ NV_REPOSITORY_COMPONENTS += userspace/units/gr/setup NV_REPOSITORY_COMPONENTS += userspace/units/gr/fs_state NV_REPOSITORY_COMPONENTS += userspace/units/gr/intr NV_REPOSITORY_COMPONENTS += userspace/units/acr +NV_REPOSITORY_COMPONENTS += userspace/units/ce NV_REPOSITORY_COMPONENTS += userspace/units/cg NV_REPOSITORY_COMPONENTS += userspace/units/sync endif diff --git a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export index 0c6261803..f0af38295 100644 --- a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export +++ b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export @@ -60,6 +60,7 @@ gm20b_priv_set_timeout_settings gm20b_priv_ring_enum_ltc gm20b_priv_ring_get_gpc_count gm20b_priv_ring_get_fbp_count +gp10b_ce_nonstall_isr gp10b_get_max_page_table_levels gp10b_mm_get_default_big_page_size gp10b_mm_get_iommu_bit @@ -79,6 +80,10 @@ gp10b_priv_ring_isr gp10b_priv_ring_decode_error_code gv100_dump_engine_status gv100_read_engine_status_info +gv11b_ce_get_num_pce +gv11b_ce_init_prod_values +gv11b_ce_mthd_buffer_fault_in_bar2_fault +gv11b_ce_stall_isr gv11b_channel_count gv11b_channel_debug_dump gv11b_channel_read_state @@ -192,6 +197,7 @@ nvgpu_big_pages_possible nvgpu_bitmap_clear nvgpu_bitmap_set nvgpu_bsearch +nvgpu_ce_init_support nvgpu_cg_blcg_fb_ltc_load_enable nvgpu_cg_blcg_fifo_load_enable nvgpu_cg_blcg_pmu_load_enable diff --git a/userspace/Makefile.sources b/userspace/Makefile.sources index 04be5e709..3feaf8d5a 100644 --- a/userspace/Makefile.sources +++ b/userspace/Makefile.sources @@ -115,5 +115,6 @@ UNITS := \ $(UNIT_SRC)/gr/intr \ $(UNIT_SRC)/gr/setup \ $(UNIT_SRC)/acr \ + $(UNIT_SRC)/ce \ $(UNIT_SRC)/cg \ $(UNIT_SRC)/sync diff --git a/userspace/required_tests.json b/userspace/required_tests.json index ba6c0b190..fd4e93a4f 100644 --- a/userspace/required_tests.json +++ b/userspace/required_tests.json @@ -353,6 +353,54 @@ "unit": "buddy_allocator", "test_level": 0 }, + { + "test": "test_free_env", + "case": "ce_free_env", + "unit": "ce", + "test_level": 0 + }, + { + "test": "test_get_num_pce", + "case": "ce_get_num_pce", + "unit": "ce", + "test_level": 0 + }, + { + "test": "test_init_prod_values", + "case": "ce_init_prod_values", + "unit": "ce", + "test_level": 0 + }, + { + "test": "test_ce_init_support", + "case": "ce_init_support", + "unit": "ce", + "test_level": 0 + }, + { + "test": "test_ce_nonstall_isr", + "case": "ce_nonstall_isr", + "unit": "ce", + "test_level": 0 + }, + { + "test": "test_setup_env", + "case": "ce_setup_env", + "unit": "ce", + "test_level": 0 + }, + { + "test": "test_ce_stall_isr", + "case": "ce_stall_isr", + "unit": "ce", + "test_level": 0 + }, + { + "test": "test_mthd_buffer_fault_in_bar2_fault", + "case": "mthd_buffer_fault_in_bar2_fault", + "unit": "ce", + "test_level": 0 + }, { "test": "test_cg", "case": "blcg_ce", diff --git a/userspace/units/ce/Makefile b/userspace/units/ce/Makefile new file mode 100644 index 000000000..b03f89119 --- /dev/null +++ b/userspace/units/ce/Makefile @@ -0,0 +1,26 @@ +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +.SUFFIXES: + +OBJS = nvgpu-ce.o +MODULE = ce + +include ../Makefile.units diff --git a/userspace/units/ce/Makefile.interface.tmk b/userspace/units/ce/Makefile.interface.tmk new file mode 100644 index 000000000..b90a13243 --- /dev/null +++ b/userspace/units/ce/Makefile.interface.tmk @@ -0,0 +1,23 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2019, NVIDIA CORPORATION. All Rights Reserved. +# +# NVIDIA CORPORATION and its licensors retain all intellectual property +# and proprietary rights in and to this software, related documentation +# and any modifications thereto. Any use, reproduction, disclosure or +# distribution of this software and related documentation without an express +# license agreement from NVIDIA CORPORATION is strictly prohibited. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=ce + +include $(NV_COMPONENT_DIR)/../Makefile.units.common.interface.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/ce/Makefile.tmk b/userspace/units/ce/Makefile.tmk new file mode 100644 index 000000000..2b30476de --- /dev/null +++ b/userspace/units/ce/Makefile.tmk @@ -0,0 +1,24 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2019, NVIDIA CORPORATION. All Rights Reserved. +# +# NVIDIA CORPORATION and its licensors retain all intellectual property +# and proprietary rights in and to this software, related documentation +# and any modifications thereto. Any use, reproduction, disclosure or +# distribution of this software and related documentation without an express +# license agreement from NVIDIA CORPORATION is strictly prohibited. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=ce +NVGPU_UNIT_SRCS=nvgpu-ce.c + +include $(NV_COMPONENT_DIR)/../Makefile.units.common.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/ce/nvgpu-ce.c b/userspace/units/ce/nvgpu-ce.c new file mode 100644 index 000000000..9bf25eacf --- /dev/null +++ b/userspace/units/ce/nvgpu-ce.c @@ -0,0 +1,363 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "nvgpu-ce.h" + +#define assert(cond) unit_assert(cond, goto fail) + +#define CE_ADDR_SPACE_START 0x00104000 +#define CE_ADDR_SPACE_SIZE 0xfff +#define NUM_INST 2 + +/* + * Mock I/O + */ + +/* + * Write callback. Forward the write access to the mock IO framework. + */ +static u32 intr_status_written[NUM_INST]; +static void writel_access_reg_fn(struct gk20a *g, + struct nvgpu_reg_access *access) +{ + if (access->addr == ce_intr_status_r(0)) { + intr_status_written[0] |= access->value; + nvgpu_posix_io_writel_reg_space(g, access->addr, + nvgpu_posix_io_readl_reg_space(g, access->addr) & + ~access->value); + } else if (access->addr == ce_intr_status_r(1)) { + intr_status_written[1] |= access->value; + nvgpu_posix_io_writel_reg_space(g, access->addr, + nvgpu_posix_io_readl_reg_space(g, access->addr) & + ~access->value); + } else { + nvgpu_posix_io_writel_reg_space(g, access->addr, access->value); + } +} + +/* + * Read callback. Get the register value from the mock IO framework. + */ +static void readl_access_reg_fn(struct gk20a *g, + struct nvgpu_reg_access *access) +{ + access->value = nvgpu_posix_io_readl_reg_space(g, access->addr); +} + +static struct nvgpu_posix_io_callbacks test_reg_callbacks = { + /* Write APIs all can use the same accessor. */ + .writel = writel_access_reg_fn, + .writel_check = writel_access_reg_fn, + .bar1_writel = writel_access_reg_fn, + .usermode_writel = writel_access_reg_fn, + + /* Likewise for the read APIs. */ + .__readl = readl_access_reg_fn, + .readl = readl_access_reg_fn, + .bar1_readl = readl_access_reg_fn, +}; + +/* + * Replacement functions that can be assigned to function pointers + */ +static void mock_void_return(struct gk20a *g) +{ + /* noop */ +} + +static void mock_mc_reset(struct gk20a *g, u32 arg1) +{ + /* noop */ +} + +static void mock_intr_unit_config(struct gk20a *g, u32 unit, bool enable) +{ + /* noop */ +} + +int test_setup_env(struct unit_module *m, + struct gk20a *g, void *args) +{ + /* Create mc register space */ + nvgpu_posix_io_init_reg_space(g); + if (nvgpu_posix_io_add_reg_space(g, CE_ADDR_SPACE_START, + CE_ADDR_SPACE_SIZE) != 0) { + unit_err(m, "%s: failed to create register space\n", + __func__); + return UNIT_FAIL; + } + (void)nvgpu_posix_register_io(g, &test_reg_callbacks); + + nvgpu_mutex_init(&g->cg_pg_lock); + g->blcg_enabled = false; + nvgpu_spinlock_init(&g->mc.intr_lock); + + return UNIT_SUCCESS; +} + +int test_free_env(struct unit_module *m, struct gk20a *g, void *args) +{ + /* Free mc register space */ + nvgpu_posix_io_delete_reg_space(g, CE_ADDR_SPACE_START); + + return UNIT_SUCCESS; +} + +int test_ce_init_support(struct unit_module *m, struct gk20a *g, void *args) +{ + int ret = UNIT_SUCCESS; + int err; + + g->fifo.num_engines = 0; + g->ops.ce.set_pce2lce_mapping = mock_void_return; + g->ops.ce.init_prod_values = mock_void_return; + g->ops.mc.reset = mock_mc_reset; + g->ops.mc.intr_nonstall_unit_config = mock_intr_unit_config; + g->ops.mc.intr_stall_unit_config = mock_intr_unit_config; + + /* test default case where all HALs are defined */ + err = nvgpu_ce_init_support(g); + if (err != 0) { + ret = UNIT_FAIL; + unit_err(m, "failed to init ce\n"); + goto done; + } + + /* test with this HAL set to NULL for branch coverage */ + g->ops.ce.set_pce2lce_mapping = NULL; + err = nvgpu_ce_init_support(g); + if (err != 0) { + ret = UNIT_FAIL; + unit_err(m, "failed to init ce\n"); + goto done; + } + + /* test with this HAL set to NULL for branch coverage */ + g->ops.ce.init_prod_values = NULL; + err = nvgpu_ce_init_support(g); + if (err != 0) { + ret = UNIT_FAIL; + unit_err(m, "failed to init ce\n"); + goto done; + } + +done: + return ret; +} + +int test_ce_stall_isr(struct unit_module *m, struct gk20a *g, void *args) +{ + int ret = UNIT_SUCCESS; + int inst_id; + u32 intr_val; + + for (inst_id = 0; inst_id < NUM_INST; inst_id++) { + intr_status_written[inst_id] = 0; + intr_val = 0x1f; /* all intr sources */ + nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id), + intr_val); + gv11b_ce_stall_isr(g, inst_id, 0); + if (intr_status_written[inst_id] != (intr_val & + ~ce_intr_status_nonblockpipe_pending_f())) { + ret = UNIT_FAIL; + unit_err(m, "intr_status not cleared, only 0x%08x\n", + intr_status_written[inst_id]); + goto done; + } + + intr_status_written[inst_id] = 0; + intr_val = 0x0; + nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id), + intr_val); + gv11b_ce_stall_isr(g, inst_id, 0); + if (intr_status_written[inst_id] != intr_val) { + ret = UNIT_FAIL; + unit_err(m, "intr_status not cleared, only 0x%08x\n", + intr_status_written[inst_id]); + goto done; + } + } + +done: + return ret; +} + +int test_ce_nonstall_isr(struct unit_module *m, struct gk20a *g, void *args) +{ + int ret = UNIT_SUCCESS; + int inst_id; + u32 intr_val; + u32 val; + + for (inst_id = 0; inst_id < NUM_INST; inst_id++) { + intr_status_written[inst_id] = 0; + intr_val = 0x1f; /* all intr sources */ + nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id), + intr_val); + val = gp10b_ce_nonstall_isr(g, inst_id, 0); + if (val != (NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE | + NVGPU_NONSTALL_OPS_POST_EVENTS)) { + ret = UNIT_FAIL; + unit_err(m, "incorrect ops returned 0x%08x\n", val); + goto done; + } + if (intr_status_written[inst_id] != + ce_intr_status_nonblockpipe_pending_f()) { + ret = UNIT_FAIL; + unit_err(m, "intr_status not cleared properly, only 0x%08x\n", + intr_status_written[inst_id]); + goto done; + } + + intr_status_written[inst_id] = 0; + intr_val = 0x0; + nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id), + intr_val); + val = gp10b_ce_nonstall_isr(g, inst_id, 0); + if (val != 0U) { + ret = UNIT_FAIL; + unit_err(m, "incorrect ops returned 0x%08x\n", val); + goto done; + } + if (intr_status_written[inst_id] != intr_val) { + ret = UNIT_FAIL; + unit_err(m, "intr_status not cleared, only 0x%08x\n", + intr_status_written[inst_id]); + goto done; + } + } + +done: + return ret; +} + +static u32 mock_get_num_lce(struct gk20a *g) +{ + return NUM_INST; +} + +int test_mthd_buffer_fault_in_bar2_fault(struct unit_module *m, struct gk20a *g, + void *args) +{ + int ret = UNIT_SUCCESS; + int inst_id; + u32 intr_val; + + g->ops.top.get_num_lce = mock_get_num_lce; + + intr_val = 0x1f; /* all intr sources */ + for (inst_id = 0; inst_id < NUM_INST; inst_id++) { + intr_status_written[inst_id] = 0; + nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id), + intr_val); + } + gv11b_ce_mthd_buffer_fault_in_bar2_fault(g); + for (inst_id = 0; inst_id < NUM_INST; inst_id++) { + if (intr_status_written[inst_id] != + ce_intr_status_mthd_buffer_fault_pending_f()) { + ret = UNIT_FAIL; + unit_err(m, "intr_status not cleared properly, only 0x%08x\n", + intr_status_written[inst_id]); + goto done; + } + } + + intr_val = 0x0; + for (inst_id = 0; inst_id < NUM_INST; inst_id++) { + intr_status_written[inst_id] = 0; + nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id), + intr_val); + } + gv11b_ce_mthd_buffer_fault_in_bar2_fault(g); + for (inst_id = 0; inst_id < NUM_INST; inst_id++) { + if (intr_status_written[inst_id] != 0) { + ret = UNIT_FAIL; + unit_err(m, "intr_status not cleared properly, only 0x%08x\n", + intr_status_written[inst_id]); + goto done; + } + } + +done: + return ret; +} + +int test_get_num_pce(struct unit_module *m, struct gk20a *g, void *args) +{ + u32 pce_map_val; /* 16 bit bitmap */ + u32 val; + + for (pce_map_val = 0; pce_map_val <= U16_MAX; pce_map_val++) { + nvgpu_posix_io_writel_reg_space(g, ce_pce_map_r(), + pce_map_val); + val = gv11b_ce_get_num_pce(g); + if (val != hweight32(pce_map_val)) { + unit_return_fail(m, "incorrect value %u\n", val); + } + } + + return UNIT_SUCCESS; +} + +int test_init_prod_values(struct unit_module *m, struct gk20a *g, void *args) +{ + int inst_id; + u32 val; + + for (inst_id = 0; inst_id < NUM_INST; inst_id++) { + /* init reg to known state */ + nvgpu_posix_io_writel_reg_space(g, ce_lce_opt_r(inst_id), 0U); + } + gv11b_ce_init_prod_values(g); + for (inst_id = 0; inst_id < NUM_INST; inst_id++) { + /* verify written correctly */ + val = nvgpu_posix_io_readl_reg_space(g, ce_lce_opt_r(inst_id)); + if (val != ce_lce_opt_force_barriers_npl__prod_f()) { + unit_return_fail(m, "value incorrect 0x%08x\n", val); + } + } + + return UNIT_SUCCESS; +} + +struct unit_module_test ce_tests[] = { + UNIT_TEST(ce_setup_env, test_setup_env, NULL, 0), + UNIT_TEST(ce_init_support, test_ce_init_support, NULL, 0), + UNIT_TEST(ce_stall_isr, test_ce_stall_isr, NULL, 0), + UNIT_TEST(ce_nonstall_isr, test_ce_nonstall_isr, NULL, 0), + UNIT_TEST(mthd_buffer_fault_in_bar2_fault, test_mthd_buffer_fault_in_bar2_fault, NULL, 0), + UNIT_TEST(ce_get_num_pce, test_get_num_pce, NULL, 0), + UNIT_TEST(ce_init_prod_values, test_init_prod_values, NULL, 0), + UNIT_TEST(ce_free_env, test_free_env, NULL, 0), +}; + +UNIT_MODULE(ce, ce_tests, UNIT_PRIO_NVGPU_TEST); diff --git a/userspace/units/ce/nvgpu-ce.h b/userspace/units/ce/nvgpu-ce.h new file mode 100644 index 000000000..92e4eac6e --- /dev/null +++ b/userspace/units/ce/nvgpu-ce.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef UNIT_NVGPU_CE_H +#define UNIT_NVGPU_CE_H + +struct gk20a; +struct unit_module; + +/** @addtogroup SWUTS-ce + * @{ + * + * Software Unit Test Specification for CE + */ + +/** + * Test specification for: test_setup_env + * + * Description: Do basic setup before starting other tests. + * + * Test Type: Other (setup) + * + * Input: None + * + * Steps: + * - Initialize reg spaces used by tests. + * - Initialize required data for cg, mc modules. + * + * Output: + * - UNIT_FAIL if encounters an error creating reg space + * - UNIT_SUCCESS otherwise + */ +int test_setup_env(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_free_env + * + * Description: Do basic setup before starting other tests. + * + * Test Type: Other (setup) + * + * Input: None + * + * Steps: + * - Free reg spaces + * + * Output: UNIT_SUCCESS always. + */ +int test_free_env(struct unit_module *m, struct gk20a *g, void *args); + +/** + * Test specification for: test_ce_init_support + * + * Description: Validate function of nvgpu_ce_init_support. + * + * Test Type: Feature based + * + * Targets: nvgpu_ce_init_support + * + * Input: test_setup_env must have been run. + * + * Steps: + * - Setup necessary mock HALs to do nothing and return success as appropriate. + * - Call nvgpu_ce_init_support and verify success is returned. + * - Set set_pce2lce_mapping and init_prod_values HAL function pointers to NULL + * for branch coverage. + * - Call nvgpu_ce_init_support and verify success is returned. + * + * Output: Returns PASS if expected result is met, FAIL otherwise. + */ +int test_ce_init_support(struct unit_module *m, struct gk20a *g, void *args); + +/** + * Test specification for: test_ce_stall_isr + * + * Description: Validate function of gv11b_ce_stall_isr. + * + * Test Type: Feature based + * + * Targets: gv11b_ce_stall_isr + * + * Input: test_setup_env must have been run. + * + * Steps: + * - Set all CE interrupt sources pending in the interrupt status reg for each + * instance. + * - Call gv11b_ce_stall_isr. + * - Verify all (and only) the stall interrupts are cleared. + * - Set no CE interrupt sources pending in the interrupt status reg for each + * instance. + * - Call gv11b_ce_stall_isr. + * - Verify no interrupts are cleared. + * + * Output: Returns PASS if expected result is met, FAIL otherwise. + */ +int test_ce_stall_isr(struct unit_module *m, struct gk20a *g, void *args); + +/** + * Test specification for: test_ce_nonstall_isr + * + * Description: Validate function of gp10b_ce_nonstall_isr. + * + * Test Type: Feature based + * + * Targets: gp10b_ce_nonstall_isr + * + * Input: test_setup_env must have been run. + * + * Steps: + * - Set all CE interrupt sources pending in the interrupt status reg for each + * instance. + * - Call gp10b_ce_nonstall_isr. + * - Verify only the nonstall interrupt is cleared and the expected ops are + * returned. + * - Set no CE interrupt sources pending in the interrupt status reg for each + * instance. + * - Call gp10b_ce_nonstall_isr. + * - Verify no interrupts are cleared and no ops are returned. + * + * Output: Returns PASS if expected result is met, FAIL otherwise. + */ +int test_ce_nonstall_isr(struct unit_module *m, struct gk20a *g, void *args); + +/** + * Test specification for: test_mthd_buffer_fault_in_bar2_fault + * + * Description: Validate function of gv11b_ce_mthd_buffer_fault_in_bar2_fault. + * + * Test Type: Feature based + * + * Targets: gv11b_ce_mthd_buffer_fault_in_bar2_fault + * + * Input: test_setup_env must have been run. + * + * Steps: + * - Set all CE interrupt sources pending in the interrupt status reg for each + * instance. + * - Call gv11b_ce_mthd_buffer_fault_in_bar2_fault. + * - Verify only the correct interrupt is cleared. + * - Set no CE interrupt sources pending in the interrupt status reg for each + * instance. + * - Call gv11b_ce_mthd_buffer_fault_in_bar2_fault. + * - Verify no interrupts are cleared. + * + * Output: Returns PASS if expected result is met, FAIL otherwise. + */ +int test_mthd_buffer_fault_in_bar2_fault(struct unit_module *m, struct gk20a *g, + void *args); + +/** + * Test specification for: test_get_num_pce + * + * Description: Validate function of gv11b_ce_get_num_pce. + * + * Test Type: Feature based + * + * Targets: gv11b_ce_get_num_pce + * + * Input: test_setup_env must have been run. + * + * Steps: + * - Loop through all possible 16 bit values for the PCE Map register. + * - For each value, write to the PCE Map register. + * - Call gv11b_ce_get_num_pce and verify the correct number of PCEs is + * returned. + * + * Output: Returns PASS if expected result is met, FAIL otherwise. + */ +int test_get_num_pce(struct unit_module *m, struct gk20a *g, void *args); + +/** + * Test specification for: test_init_prod_values + * + * Description: Validate function of gv11b_ce_init_prod_values. + * + * Test Type: Feature based + * + * Targets: gv11b_ce_init_prod_values + * + * Input: test_setup_env must have been run. + * + * Steps: + * - Clear the LCE Options register for all instances. + * - Call gv11b_ce_init_prod_values. + * - Verify all instances of the LCE Options register are set properly. + * + * Output: Returns PASS if expected result is met, FAIL otherwise. + */ +int test_init_prod_values(struct unit_module *m, struct gk20a *g, void *args); + +#endif /* UNIT_NVGPU_CE_H */ \ No newline at end of file