gpu: nvgpu: compiled out non-safe devctls

The following DEVCTLs not needed in safety build
Compiled out below DEVCTLs for safety build

 * NVGPU_GPU_DEVCTL_SET_THERM_ALERT_LIMIT
 * NVGPU_GPU_DEVCTL_GET_TPC_EXCEPTION_EN_STATUS
 * NVGPU_GPU_DEVCTL_GET_CPU_TIME_CORRELATION_INFO

Also added config flag CONFIG_NVGPU_IOCTL_NON_FUSA

JIRA NVGPU-3768

Change-Id: Ia233d0aac8201268524581f588d97390a913ab9c
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159398
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/pmu/therm/thrmpmu.c

@@ -34,6 +34,7 @@ struct therm_pmucmdhandler_params {
 	u32 success;
 };
 
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 static void therm_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
 			void *param, u32 status)
 {
@@ -53,6 +54,7 @@ static void therm_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
 		phandlerparams->success = 1;
 	}
 }
+#endif
 
 int therm_send_pmgr_tables_to_pmu(struct gk20a *g)
 {
@@ -86,6 +88,7 @@ exit:
 	return status;
 }
 
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 static int therm_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
 		struct pmu_payload *payload,
 		u32 queue_id, pmu_callback callback, void *cb_param)
@@ -257,6 +260,7 @@ int nvgpu_therm_configure_therm_alert(struct gk20a *g, struct nvgpu_pmu *pmu)
 exit:
 	return status;
 }
+#endif
 
 void nvgpu_pmu_therm_rpc_handler(struct gk20a *g, struct nvgpu_pmu *pmu,
 		struct nv_pmu_rpc_header *rpc)

drivers/gpu/nvgpu/common/ptimer/ptimer.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -20,6 +20,7 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 #include <nvgpu/ptimer.h>
 #include <nvgpu/timers.h>
 #include <nvgpu/gk20a.h>
@@ -50,3 +51,4 @@ end:
 	gk20a_idle(g);
 	return err;
 }
+#endif

drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -752,7 +752,9 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 	.ptimer = {
 		.isr = NULL,
 		.read_ptimer = vgpu_read_ptimer,
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 		.get_timestamps_zipper = vgpu_get_timestamps_zipper,
+#endif
 	},
 #if defined(CONFIG_NVGPU_CYCLESTATS)
 	.css = {

drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c

@@ -1497,6 +1497,7 @@ int vgpu_gr_set_preemption_mode(struct nvgpu_channel *ch,
 	return err;
 }
 
+#ifdef CONFIG_NVGPU_DEBUGGER
 u64 vgpu_gr_gk20a_tpc_enabled_exceptions(struct gk20a *g)
 {
 	struct tegra_vgpu_cmd_msg msg = {};
@@ -1518,3 +1519,4 @@ u64 vgpu_gr_gk20a_tpc_enabled_exceptions(struct gk20a *g)
 	tpc_exception_en = p->tpc_exception_en_sm_mask;
 	return tpc_exception_en;
 }
+#endif

drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h

@@ -93,6 +93,8 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info);
 void vgpu_gr_handle_sm_esr_event(struct gk20a *g,
 			struct tegra_vgpu_sm_esr_info *info);
 int vgpu_init_gr_support(struct gk20a *g);
+#ifdef CONFIG_NVGPU_DEBUGGER
 u64 vgpu_gr_gk20a_tpc_enabled_exceptions(struct gk20a *g);
+#endif
 
 #endif /* NVGPU_GR_VGPU_H */

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -443,8 +443,10 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 			.flush_channel_tlb = nvgpu_gr_intr_flush_channel_tlb,
 			.get_sm_no_lock_down_hww_global_esr_mask =
 				gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
+#ifdef CONFIG_NVGPU_DEBUGGER
 			.tpc_enabled_exceptions =
 				vgpu_gr_gk20a_tpc_enabled_exceptions,
+#endif
 		},
 	},
 	.gpu_class = {
@@ -847,7 +849,9 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 	.ptimer = {
 		.isr = NULL,
 		.read_ptimer = vgpu_read_ptimer,
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 		.get_timestamps_zipper = vgpu_get_timestamps_zipper,
+#endif
 	},
 #if defined(CONFIG_NVGPU_CYCLESTATS)
 	.css = {