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gpu: nvgpu: compiled out non-safe devctls

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The following DEVCTLs not needed in safety build
Compiled out below DEVCTLs for safety build

 * NVGPU_GPU_DEVCTL_SET_THERM_ALERT_LIMIT
 * NVGPU_GPU_DEVCTL_GET_TPC_EXCEPTION_EN_STATUS
 * NVGPU_GPU_DEVCTL_GET_CPU_TIME_CORRELATION_INFO

Also added config flag CONFIG_NVGPU_IOCTL_NON_FUSA

JIRA NVGPU-3768

Change-Id: Ia233d0aac8201268524581f588d97390a913ab9c
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159398
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kadamati
2019-07-23 15:19:22 +05:30
committed by mobile promotions
parent 5798894b68
commit 77051a8c86
17 changed files with 51 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -456,8 +456,10 @@ static const struct gpu_ops gm20b_ops = {
gm20b_gr_intr_get_sm_hww_global_esr,
.get_sm_no_lock_down_hww_global_esr_mask =
gm20b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
#ifdef CONFIG_NVGPU_DEBUGGER
.tpc_enabled_exceptions =
gm20b_gr_intr_tpc_enabled_exceptions,
#endif
},
.falcon = {
.read_fecs_ctxsw_mailbox =
@@ -959,7 +961,9 @@ static const struct gpu_ops gm20b_ops = {
.ptimer = {
.isr = gk20a_ptimer_isr,
.read_ptimer = gk20a_read_ptimer,
#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
#endif
},
#if defined(CONFIG_NVGPU_CYCLESTATS)
.css = {

4
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -523,8 +523,10 @@ static const struct gpu_ops gp10b_ops = {
gm20b_gr_intr_get_sm_hww_global_esr,
.get_sm_no_lock_down_hww_global_esr_mask =
gm20b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
#ifdef CONFIG_NVGPU_DEBUGGER
.tpc_enabled_exceptions =
gm20b_gr_intr_tpc_enabled_exceptions,
#endif
},
.falcon = {
.read_fecs_ctxsw_mailbox =
@@ -1048,7 +1050,9 @@ static const struct gpu_ops gp10b_ops = {
.ptimer = {
.isr = gk20a_ptimer_isr,
.read_ptimer = gk20a_read_ptimer,
#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
#endif
},
#if defined(CONFIG_NVGPU_CYCLESTATS)
.css = {

4
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -624,8 +624,10 @@ static const struct gpu_ops gv11b_ops = {
gv11b_gr_intr_get_sm_hww_global_esr,
.get_sm_no_lock_down_hww_global_esr_mask =
gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
#ifdef CONFIG_NVGPU_DEBUGGER
.tpc_enabled_exceptions =
gm20b_gr_intr_tpc_enabled_exceptions,
#endif
.get_ctxsw_checksum_mismatch_mailbox_val =
gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val,
},
@@ -1221,7 +1223,9 @@ static const struct gpu_ops gv11b_ops = {
.ptimer = {
.isr = gk20a_ptimer_isr,
.read_ptimer = gk20a_read_ptimer,
#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
#endif
},
#if defined(CONFIG_NVGPU_CYCLESTATS)
.css = {

4
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -665,8 +665,10 @@ static const struct gpu_ops tu104_ops = {
gv11b_gr_intr_get_sm_hww_global_esr,
.get_sm_no_lock_down_hww_global_esr_mask =
gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
#ifdef CONFIG_NVGPU_DEBUGGER
.tpc_enabled_exceptions =
gm20b_gr_intr_tpc_enabled_exceptions,
#endif
},
.falcon = {
.handle_fecs_ecc_error =
@@ -1267,7 +1269,9 @@ static const struct gpu_ops tu104_ops = {
.ptimer = {
.isr = gk20a_ptimer_isr,
.read_ptimer = gk20a_read_ptimer,
#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
#endif
},
#if defined(CONFIG_NVGPU_CYCLESTATS)
.css = {