gpu: nvgpu: compiled out non-safe devctls

The following DEVCTLs not needed in safety build
Compiled out below DEVCTLs for safety build

 * NVGPU_GPU_DEVCTL_SET_THERM_ALERT_LIMIT
 * NVGPU_GPU_DEVCTL_GET_TPC_EXCEPTION_EN_STATUS
 * NVGPU_GPU_DEVCTL_GET_CPU_TIME_CORRELATION_INFO

Also added config flag CONFIG_NVGPU_IOCTL_NON_FUSA

JIRA NVGPU-3768

Change-Id: Ia233d0aac8201268524581f588d97390a913ab9c
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159398
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -48,6 +48,7 @@ ccflags-y += -DCONFIG_NVGPU_SYSFS
 ccflags-y += -DCONFIG_NVGPU_CLK_ARB
 ccflags-y += -DCONFIG_NVGPU_FALCON_DEBUG
 ccflags-y += -DCONFIG_NVGPU_FALCON_NON_FUSA
+ccflags-y += -DCONFIG_NVGPU_IOCTL_NON_FUSA
 
 ifeq ($(CONFIG_NVGPU_LOGGING),y)
 ccflags-y += -DCONFIG_NVGPU_LOGGING=1

drivers/gpu/nvgpu/Makefile.shared.configs

@@ -172,6 +172,8 @@ NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_CLK_ARB
 
 NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_FALCON_NON_FUSA
 
+NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_IOCTL_NON_FUSA
+
 endif
 endif
 

drivers/gpu/nvgpu/common/pmu/therm/thrmpmu.c

@@ -34,6 +34,7 @@ struct therm_pmucmdhandler_params {
 	u32 success;
 };
 
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 static void therm_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
 			void *param, u32 status)
 {
@@ -53,6 +54,7 @@ static void therm_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
 		phandlerparams->success = 1;
 	}
 }
+#endif
 
 int therm_send_pmgr_tables_to_pmu(struct gk20a *g)
 {
@@ -86,6 +88,7 @@ exit:
 	return status;
 }
 
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 static int therm_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
 		struct pmu_payload *payload,
 		u32 queue_id, pmu_callback callback, void *cb_param)
@@ -257,6 +260,7 @@ int nvgpu_therm_configure_therm_alert(struct gk20a *g, struct nvgpu_pmu *pmu)
 exit:
 	return status;
 }
+#endif
 
 void nvgpu_pmu_therm_rpc_handler(struct gk20a *g, struct nvgpu_pmu *pmu,
 		struct nv_pmu_rpc_header *rpc)

drivers/gpu/nvgpu/common/ptimer/ptimer.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -20,6 +20,7 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 #include <nvgpu/ptimer.h>
 #include <nvgpu/timers.h>
 #include <nvgpu/gk20a.h>
@@ -50,3 +51,4 @@ end:
 	gk20a_idle(g);
 	return err;
 }
+#endif

drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -752,7 +752,9 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 	.ptimer = {
 		.isr = NULL,
 		.read_ptimer = vgpu_read_ptimer,
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 		.get_timestamps_zipper = vgpu_get_timestamps_zipper,
+#endif
 	},
 #if defined(CONFIG_NVGPU_CYCLESTATS)
 	.css = {

drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c

@@ -1497,6 +1497,7 @@ int vgpu_gr_set_preemption_mode(struct nvgpu_channel *ch,
 	return err;
 }
 
+#ifdef CONFIG_NVGPU_DEBUGGER
 u64 vgpu_gr_gk20a_tpc_enabled_exceptions(struct gk20a *g)
 {
 	struct tegra_vgpu_cmd_msg msg = {};
@@ -1518,3 +1519,4 @@ u64 vgpu_gr_gk20a_tpc_enabled_exceptions(struct gk20a *g)
 	tpc_exception_en = p->tpc_exception_en_sm_mask;
 	return tpc_exception_en;
 }
+#endif

drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h

@@ -93,6 +93,8 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info);
 void vgpu_gr_handle_sm_esr_event(struct gk20a *g,
 			struct tegra_vgpu_sm_esr_info *info);
 int vgpu_init_gr_support(struct gk20a *g);
+#ifdef CONFIG_NVGPU_DEBUGGER
 u64 vgpu_gr_gk20a_tpc_enabled_exceptions(struct gk20a *g);
+#endif
 
 #endif /* NVGPU_GR_VGPU_H */

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -443,8 +443,10 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 			.flush_channel_tlb = nvgpu_gr_intr_flush_channel_tlb,
 			.get_sm_no_lock_down_hww_global_esr_mask =
 				gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
+#ifdef CONFIG_NVGPU_DEBUGGER
 			.tpc_enabled_exceptions =
 				vgpu_gr_gk20a_tpc_enabled_exceptions,
+#endif
 		},
 	},
 	.gpu_class = {
@@ -847,7 +849,9 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 	.ptimer = {
 		.isr = NULL,
 		.read_ptimer = vgpu_read_ptimer,
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 		.get_timestamps_zipper = vgpu_get_timestamps_zipper,
+#endif
 	},
 #if defined(CONFIG_NVGPU_CYCLESTATS)
 	.css = {

drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.h

@@ -80,6 +80,8 @@ u32 gm20b_gr_intr_get_sm_hww_global_esr(struct gk20a *g, u32 gpc, u32 tpc,
 		u32 sm);
 u32 gm20b_gr_intr_get_sm_hww_warp_esr(struct gk20a *g, u32 gpc, u32 tpc, u32 sm);
 u32 gm20b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g);
+#ifdef CONFIG_NVGPU_DEBUGGER
 u64 gm20b_gr_intr_tpc_enabled_exceptions(struct gk20a *g);
+#endif
 
 #endif /* NVGPU_GR_INTR_GM20B_H */

drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b_fusa.c

@@ -411,6 +411,7 @@ u32 gm20b_gr_intr_nonstall_isr(struct gk20a *g)
 	return ops;
 }
 
+#ifdef CONFIG_NVGPU_DEBUGGER
 u64 gm20b_gr_intr_tpc_enabled_exceptions(struct gk20a *g)
 {
 	u32 sm_id;
@@ -440,3 +441,4 @@ u64 gm20b_gr_intr_tpc_enabled_exceptions(struct gk20a *g)
 
 	return tpc_exception_en;
 }
+#endif

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -456,8 +456,10 @@ static const struct gpu_ops gm20b_ops = {
 				gm20b_gr_intr_get_sm_hww_global_esr,
 			.get_sm_no_lock_down_hww_global_esr_mask =
 				gm20b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
+#ifdef CONFIG_NVGPU_DEBUGGER
 			.tpc_enabled_exceptions =
 				gm20b_gr_intr_tpc_enabled_exceptions,
+#endif
 		},
 		.falcon = {
 			.read_fecs_ctxsw_mailbox =
@@ -959,7 +961,9 @@ static const struct gpu_ops gm20b_ops = {
 	.ptimer = {
 		.isr = gk20a_ptimer_isr,
 		.read_ptimer = gk20a_read_ptimer,
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 		.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
+#endif
 	},
 #if defined(CONFIG_NVGPU_CYCLESTATS)
 	.css = {

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -523,8 +523,10 @@ static const struct gpu_ops gp10b_ops = {
 				gm20b_gr_intr_get_sm_hww_global_esr,
 			.get_sm_no_lock_down_hww_global_esr_mask =
 				gm20b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
+#ifdef CONFIG_NVGPU_DEBUGGER
 			.tpc_enabled_exceptions =
 				gm20b_gr_intr_tpc_enabled_exceptions,
+#endif
 		},
 		.falcon = {
 			.read_fecs_ctxsw_mailbox =
@@ -1048,7 +1050,9 @@ static const struct gpu_ops gp10b_ops = {
 	.ptimer = {
 		.isr = gk20a_ptimer_isr,
 		.read_ptimer = gk20a_read_ptimer,
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 		.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
+#endif
 	},
 #if defined(CONFIG_NVGPU_CYCLESTATS)
 	.css = {

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -624,8 +624,10 @@ static const struct gpu_ops gv11b_ops = {
 				gv11b_gr_intr_get_sm_hww_global_esr,
 			.get_sm_no_lock_down_hww_global_esr_mask =
 				gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
+#ifdef CONFIG_NVGPU_DEBUGGER
 			.tpc_enabled_exceptions =
 				gm20b_gr_intr_tpc_enabled_exceptions,
+#endif
 			.get_ctxsw_checksum_mismatch_mailbox_val =
 				gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val,
 		},
@@ -1221,7 +1223,9 @@ static const struct gpu_ops gv11b_ops = {
 	.ptimer = {
 		.isr = gk20a_ptimer_isr,
 		.read_ptimer = gk20a_read_ptimer,
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 		.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
+#endif
 	},
 #if defined(CONFIG_NVGPU_CYCLESTATS)
 	.css = {

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -665,8 +665,10 @@ static const struct gpu_ops tu104_ops = {
 				gv11b_gr_intr_get_sm_hww_global_esr,
 			.get_sm_no_lock_down_hww_global_esr_mask =
 				gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
+#ifdef CONFIG_NVGPU_DEBUGGER
 			.tpc_enabled_exceptions =
 				gm20b_gr_intr_tpc_enabled_exceptions,
+#endif
 		},
 		.falcon = {
 			.handle_fecs_ecc_error =
@@ -1267,7 +1269,9 @@ static const struct gpu_ops tu104_ops = {
 	.ptimer = {
 		.isr = gk20a_ptimer_isr,
 		.read_ptimer = gk20a_read_ptimer,
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 		.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
+#endif
 	},
 #if defined(CONFIG_NVGPU_CYCLESTATS)
 	.css = {

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -897,7 +897,9 @@ struct gpu_ops {
 				u32 offset);
 			u32 (*get_sm_no_lock_down_hww_global_esr_mask)(
 				struct gk20a *g);
+#ifdef CONFIG_NVGPU_DEBUGGER
 			u64 (*tpc_enabled_exceptions)(struct gk20a *g);
+#endif
 			u32 (*get_ctxsw_checksum_mismatch_mailbox_val)(void);
 		} intr;
 	} gr;
@@ -1400,7 +1402,9 @@ struct gpu_ops {
 		int (*get_internal_sensor_curr_temp)(struct gk20a *g, u32 *temp_f24_8);
 		void (*get_internal_sensor_limits)(s32 *max_24_8,
 							s32 *min_24_8);
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 		int (*configure_therm_alert)(struct gk20a *g, s32 curr_warn_temp);
+#endif
 		void (*throttle_enable)(struct gk20a *g, u32 val);
 		u32 (*throttle_disable)(struct gk20a *g);
 		void (*idle_slowdown_enable)(struct gk20a *g, u32 val);
@@ -1643,9 +1647,11 @@ struct gpu_ops {
 	struct {
 		void (*isr)(struct gk20a *g);
 		int (*read_ptimer)(struct gk20a *g, u64 *value);
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 		int (*get_timestamps_zipper)(struct gk20a *g,
 			u32 source_id, u32 count,
 			struct nvgpu_cpu_time_correlation_sample *samples);
+#endif
 	} ptimer;
 
 	struct {

drivers/gpu/nvgpu/include/nvgpu/pmu/therm.h

@@ -34,7 +34,9 @@ int nvgpu_therm_domain_sw_setup(struct gk20a *g, struct nvgpu_pmu *pmu);
 int nvgpu_therm_domain_pmu_setup(struct gk20a *g, struct nvgpu_pmu *pmu);
 int nvgpu_therm_pmu_init_pmupstate(struct gk20a *g, struct nvgpu_pmu *pmu);
 void nvgpu_therm_pmu_free_pmupstate(struct gk20a *g, struct nvgpu_pmu *pmu);
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 int nvgpu_therm_configure_therm_alert(struct gk20a *g, struct nvgpu_pmu *pmu);
+#endif
 void nvgpu_pmu_therm_rpc_handler(struct gk20a *g, struct nvgpu_pmu *pmu,
 				 struct nv_pmu_rpc_header *rpc);
 

drivers/gpu/nvgpu/include/nvgpu/ptimer.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -49,7 +49,9 @@ static inline u32 scale_ptimer(u32 timeout , u32 scale10x)
 	}
 }
 
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 int nvgpu_get_timestamps_zipper(struct gk20a *g,
 		u32 source_id, u32 count,
 		struct nvgpu_cpu_time_correlation_sample *samples);
+#endif /* CONFIG_NVGPU_IOCTL_NON_FUSA */
 #endif