From 773c27dab5c172bb16ae0899bd448a99a7d48f31 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Tue, 28 May 2019 16:03:21 -0700 Subject: [PATCH] gpu: nvgpu: fix CERT-C issue in common gr falcon Fix CERT INT30-c issue in gr falcon driver replacing u32 arithmetic operation with nvgpu_safe_add_u32. Also replaced SZ_256 with 256U to avoid mixed math calculation with u32 and UL. JIRA NVGPU-3413 Change-Id: If4f52845a78b7dc0c7936040d759471ba2e5ffc1 Signed-off-by: Seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/2126840 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/gr_falcon.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/common/gr/gr_falcon.c b/drivers/gpu/nvgpu/common/gr/gr_falcon.c index 729d648b7..d48049919 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_falcon.c +++ b/drivers/gpu/nvgpu/common/gr/gr_falcon.c @@ -237,9 +237,12 @@ static int nvgpu_gr_falcon_init_ctxsw_ucode_vaspace(struct gk20a *g, static void nvgpu_gr_falcon_init_ctxsw_ucode_segment( struct nvgpu_ctxsw_ucode_segment *p_seg, u32 *offset, u32 size) { + u32 ucode_offset; + p_seg->offset = *offset; p_seg->size = size; - *offset = ALIGN(*offset + size, SZ_256); + ucode_offset = nvgpu_safe_add_u32(*offset, size); + *offset = ALIGN(ucode_offset, 256U); } static void nvgpu_gr_falcon_init_ctxsw_ucode_segments(