gpu: nvgpu: Update runlist_update() to take runlist ptr

Update the nvgpu_runlist_update_for_channel() function:

  - Rename it to nvgpu_runlist_update()
  - Have it take a pointer to the runlist to update instead
    of a runlist ID. For the most part this makes the code
    better but there's a few places where it's worse (for
    now).

This starts the slow and painful process of moving away from
the non-runlist code using runlist IDs in many places it should
not.

Most of this patch is just fixing compilation problems with
the minor header updates.

JIRA NVGPU-6425

Change-Id: Id9885fe655d1d750625a1c8aceda9e67a2cbdb7a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2470304
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit

drivers/gpu/nvgpu/hal/fifo/preempt_gv11b_fusa.c

@@ -312,27 +312,27 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id,
 		 unsigned int id_type)
 {
 	struct nvgpu_fifo *f = &g->fifo;
+	struct nvgpu_runlist *rl;
 	unsigned long runlist_served_pbdmas;
 	unsigned long runlist_served_engines;
 	unsigned long bit;
 	u32 pbdma_id;
 	u32 engine_id;
-	u32 runlist_id;
 	int err, ret = 0;
 	u32 tsgid;
 
 	if (id_type == ID_TYPE_TSG) {
-		runlist_id = f->tsg[id].runlist_id;
+		rl = f->runlists[f->tsg[id].runlist_id];
 		tsgid = id;
 	} else {
-		runlist_id = f->channel[id].runlist_id;
+		rl = f->channel[id].runlist;
 		tsgid = f->channel[id].tsgid;
 	}
 
 	nvgpu_log_info(g, "Check preempt pending for tsgid = %u", tsgid);
 
-	runlist_served_pbdmas = f->runlists[runlist_id]->pbdma_bitmask;
-	runlist_served_engines = f->runlists[runlist_id]->eng_bitmask;
+	runlist_served_pbdmas = rl->pbdma_bitmask;
+	runlist_served_engines = rl->eng_bitmask;
 
 	for_each_set_bit(bit, &runlist_served_pbdmas,
 			 nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA)) {
@@ -344,13 +344,13 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id,
 		}
 	}
 
-	f->runlists[runlist_id]->reset_eng_bitmask = 0U;
+	rl->reset_eng_bitmask = 0U;
 
 	for_each_set_bit(bit, &runlist_served_engines, f->max_engines) {
 		engine_id = U32(bit);
 		err = gv11b_fifo_preempt_poll_eng(g,
 			tsgid, engine_id,
-			&f->runlists[runlist_id]->reset_eng_bitmask);
+			&rl->reset_eng_bitmask);
 		if ((err != 0) && (ret == 0)) {
 			ret = err;
 		}

drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.c

@@ -52,8 +52,7 @@ int gk20a_fifo_reschedule_preempt_next(struct nvgpu_channel *ch,
 		bool wait_preempt)
 {
 	struct gk20a *g = ch->g;
-	struct nvgpu_runlist *runlist =
-		g->fifo.runlists[ch->runlist_id];
+	struct nvgpu_runlist *runlist = ch->runlist;
 	int ret = 0;
 	u32 fecsstat0 = 0, fecsstat1 = 0;
 	u32 preempt_id;

drivers/gpu/nvgpu/hal/fifo/usermode_tu104.c

@@ -26,6 +26,7 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/io_usermode.h>
+#include <nvgpu/runlist.h>
 
 #include "usermode_tu104.h"
 
@@ -59,13 +60,13 @@ u32 tu104_usermode_doorbell_token(struct nvgpu_channel *ch)
 	u32 hw_chid = f->channel_base + ch->chid;
 
 	return ctrl_doorbell_vector_f(hw_chid) |
-			ctrl_doorbell_runlist_id_f(ch->runlist_id);
+			ctrl_doorbell_runlist_id_f(ch->runlist->runlist_id);
 }
 
 void tu104_usermode_ring_doorbell(struct nvgpu_channel *ch)
 {
 	nvgpu_log_info(ch->g, "channel ring door bell %d, runlist %d",
-			ch->chid, ch->runlist_id);
+			ch->chid, ch->runlist->runlist_id);
 
 	nvgpu_usermode_writel(ch->g, func_doorbell_r(),
 				ch->g->ops.usermode.doorbell_token(ch));

drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.c

@@ -44,6 +44,7 @@
 #include <nvgpu/engines.h>
 #include <nvgpu/engine_status.h>
 #include <nvgpu/preempt.h>
+#include <nvgpu/runlist.h>
 
 #include "gr_gk20a.h"
 #include "gr_gp10b.h"
@@ -402,7 +403,7 @@ static int gr_gp10b_disable_channel_or_tsg(struct gk20a *g, struct nvgpu_channel
 		return ret;
 	}
 
-	ret = g->ops.runlist.reload(g, fault_ch->runlist_id, true, false);
+	ret = g->ops.runlist.reload(g, fault_ch->runlist, true, false);
 	if (ret != 0) {
 		nvgpu_err(g, "CILP: failed to restart runlist 0!");
 		return ret;

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -684,7 +684,7 @@ static const struct gops_ramin gm20b_ops_ramin = {
 };
 
 static const struct gops_runlist gm20b_ops_runlist = {
-	.update_for_channel = nvgpu_runlist_update_for_channel,
+	.update = nvgpu_runlist_update,
 	.reload = nvgpu_runlist_reload,
 	.count_max = gk20a_runlist_count_max,
 	.entry_size = gk20a_runlist_entry_size,

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -769,7 +769,7 @@ static const struct gops_runlist gp10b_ops_runlist = {
 	.reschedule = gk20a_runlist_reschedule,
 	.reschedule_preempt_next_locked = gk20a_fifo_reschedule_preempt_next,
 #endif
-	.update_for_channel = nvgpu_runlist_update_for_channel,
+	.update = nvgpu_runlist_update,
 	.reload = nvgpu_runlist_reload,
 	.count_max = gk20a_runlist_count_max,
 	.entry_size = gk20a_runlist_entry_size,

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -943,7 +943,7 @@ static const struct gops_runlist gv11b_ops_runlist = {
 	.reschedule = gv11b_runlist_reschedule,
 	.reschedule_preempt_next_locked = gk20a_fifo_reschedule_preempt_next,
 #endif
-	.update_for_channel = nvgpu_runlist_update_for_channel,
+	.update = nvgpu_runlist_update,
 	.reload = nvgpu_runlist_reload,
 	.count_max = gv11b_runlist_count_max,
 	.entry_size = gv11b_runlist_entry_size,

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -994,7 +994,7 @@ static const struct gops_ramin tu104_ops_ramin = {
 };
 
 static const struct gops_runlist tu104_ops_runlist = {
-	.update_for_channel = nvgpu_runlist_update_for_channel,
+	.update = nvgpu_runlist_update,
 	.reload = nvgpu_runlist_reload,
 	.count_max = tu104_runlist_count_max,
 	.entry_size = tu104_runlist_entry_size,

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c

@@ -546,7 +546,7 @@ static const struct gops_ramin vgpu_gp10b_ops_ramin = {
 
 static const struct gops_runlist vgpu_gp10b_ops_runlist = {
 	.reschedule = NULL,
-	.update_for_channel = vgpu_runlist_update_for_channel,
+	.update = vgpu_runlist_update,
 	.reload = vgpu_runlist_reload,
 	.count_max = gk20a_runlist_count_max,
 	.entry_size = vgpu_runlist_entry_size,

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c

@@ -649,7 +649,7 @@ static const struct gops_ramin vgpu_gv11b_ops_ramin = {
 
 static const struct gops_runlist vgpu_gv11b_ops_runlist = {
 	.reschedule = NULL,
-	.update_for_channel = vgpu_runlist_update_for_channel,
+	.update = vgpu_runlist_update,
 	.reload = vgpu_runlist_reload,
 	.count_max = gv11b_runlist_count_max,
 	.entry_size = vgpu_runlist_entry_size,