From 77f0ab6583c5c84384b7289b246b6526ee982fbd Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Tue, 15 Jun 2021 13:58:20 -0700 Subject: [PATCH] gpu: nvgpu: remove gpu_va update_hwpm_ctxsw_mode Since gpu server can noew allocate va itself, update_hwpm_ctxsw_mode does not need to fixed map pm ctx anymore. Jira GVSCI-10977 Change-Id: If592c8a2eb6dbfd7d922c79c87871162e9d8d8a4 Signed-off-by: Richard Zhao Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2546192 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/ctx.c | 6 ++--- drivers/gpu/nvgpu/common/profiler/profiler.c | 4 +-- drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.c | 27 +------------------ drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.h | 2 -- drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c | 18 +------------ drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h | 2 +- .../common/vgpu/profiler/profiler_vgpu.c | 17 ------------ drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c | 4 +-- drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/gops/gr.h | 1 - drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h | 3 +-- .../gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | 1 - drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 2 +- 13 files changed, 11 insertions(+), 78 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/ctx.c b/drivers/gpu/nvgpu/common/gr/ctx.c index 3d49f7e9c..f2897a1a6 100644 --- a/drivers/gpu/nvgpu/common/gr/ctx.c +++ b/drivers/gpu/nvgpu/common/gr/ctx.c @@ -982,8 +982,7 @@ void nvgpu_gr_ctx_set_patch_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, int nvgpu_gr_ctx_alloc_pm_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, struct nvgpu_gr_ctx_desc *gr_ctx_desc, - struct vm_gk20a *vm, - u64 gpu_va) + struct vm_gk20a *vm) { struct pm_ctx_desc *pm_ctx = &gr_ctx->pm_ctx; int err; @@ -1000,9 +999,8 @@ int nvgpu_gr_ctx_alloc_pm_ctx(struct gk20a *g, return err; } - pm_ctx->mem.gpu_va = nvgpu_gmmu_map_fixed(vm, + pm_ctx->mem.gpu_va = nvgpu_gmmu_map(vm, &pm_ctx->mem, - gpu_va, pm_ctx->mem.size, NVGPU_VM_MAP_CACHEABLE, gk20a_mem_flag_none, true, diff --git a/drivers/gpu/nvgpu/common/profiler/profiler.c b/drivers/gpu/nvgpu/common/profiler/profiler.c index 4bff174f1..7fe711c69 100644 --- a/drivers/gpu/nvgpu/common/profiler/profiler.c +++ b/drivers/gpu/nvgpu/common/profiler/profiler.c @@ -373,7 +373,7 @@ static int nvgpu_profiler_bind_hwpm_common(struct gk20a *g, u32 gr_instance_id, g->ops.perf.init_hwpm_pmm_register(g); } else { err = g->ops.gr.update_hwpm_ctxsw_mode( - g, gr_instance_id, tsg, 0, mode); + g, gr_instance_id, tsg, mode); } return err; @@ -394,7 +394,7 @@ int nvgpu_profiler_unbind_hwpm(struct gk20a *g, u32 gr_instance_id, if (is_ctxsw) { err = g->ops.gr.update_hwpm_ctxsw_mode( - g, gr_instance_id, tsg, 0, mode); + g, gr_instance_id, tsg, mode); } return err; diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.c index a7fac2fcd..9a5e2b555 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.c @@ -56,29 +56,4 @@ void vgpu_gr_free_gr_ctx(struct gk20a *g, WARN_ON(err || msg.ret); (void) memset(gr_ctx, 0, sizeof(*gr_ctx)); -} - -int vgpu_gr_alloc_pm_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, - struct vm_gk20a *vm) -{ - struct pm_ctx_desc *pm_ctx = &gr_ctx->pm_ctx; - struct nvgpu_gr_hwpm_map *gr_hwpm_map = nvgpu_gr_get_hwpm_map_ptr(g); - - nvgpu_log_fn(g, " "); - - if (pm_ctx->mem.gpu_va != 0ULL) { - return 0; - } - - pm_ctx->mem.gpu_va = nvgpu_vm_alloc_va(vm, - nvgpu_gr_hwpm_map_get_size(gr_hwpm_map), - GMMU_PAGE_SIZE_KERNEL); - - if (!pm_ctx->mem.gpu_va) { - nvgpu_err(g, "failed to map pm ctxt buffer"); - return -ENOMEM; - } - - pm_ctx->mem.size = nvgpu_gr_hwpm_map_get_size(gr_hwpm_map); - return 0; -} +} \ No newline at end of file diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.h b/drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.h index 40cc4a88f..9f102d998 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.h +++ b/drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.h @@ -29,7 +29,5 @@ struct vm_gk20a; void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, struct nvgpu_gr_ctx *gr_ctx); -int vgpu_gr_alloc_pm_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, - struct vm_gk20a *vm); #endif diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c index 148e92f65..4475dd8f4 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c @@ -799,7 +799,7 @@ int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g, } int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, - u32 gr_instance_id, struct nvgpu_tsg *tsg, u64 gpu_va, u32 mode) + u32 gr_instance_id, struct nvgpu_tsg *tsg, u32 mode) { struct nvgpu_gr_ctx *gr_ctx; struct tegra_vgpu_cmd_msg msg; @@ -808,11 +808,6 @@ int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, nvgpu_log_fn(g, " "); - if (gpu_va) { - nvgpu_err(g, "gpu_va suppose to be allocated by this function."); - return -EINVAL; - } - gr_ctx = tsg->gr_ctx; if (mode == NVGPU_GR_CTX_HWPM_CTXSW_MODE_CTXSW) { @@ -844,20 +839,9 @@ int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, return -EINVAL; } - if (mode != NVGPU_GR_CTX_HWPM_CTXSW_MODE_NO_CTXSW) { - /* Allocate buffer if necessary */ - err = vgpu_gr_alloc_pm_ctx(g, tsg->gr_ctx, tsg->vm); - if (err != 0) { - nvgpu_err(g, - "failed to allocate pm ctxt buffer"); - return err; - } - } - msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE; msg.handle = vgpu_get_handle(g); p->tsg_id = tsg->tsgid; - p->gpu_va = nvgpu_gr_ctx_get_pm_ctx_mem(gr_ctx)->gpu_va; err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); WARN_ON(err || msg.ret); diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h index 5a2fe2d7a..12aaa60fa 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h +++ b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h @@ -72,7 +72,7 @@ int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g, int vgpu_gr_set_sm_debug_mode(struct gk20a *g, struct nvgpu_channel *ch, u64 sms, bool enable); int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, - u32 gr_instance_id, struct nvgpu_tsg *tsg, u64 gpu_va, u32 mode); + u32 gr_instance_id, struct nvgpu_tsg *tsg, u32 mode); int vgpu_gr_clear_sm_error_state(struct gk20a *g, struct nvgpu_channel *ch, u32 sm_id); int vgpu_gr_suspend_contexts(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/common/vgpu/profiler/profiler_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/profiler/profiler_vgpu.c index f943482b8..6196bd5c9 100644 --- a/drivers/gpu/nvgpu/common/vgpu/profiler/profiler_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/profiler/profiler_vgpu.c @@ -44,14 +44,6 @@ int vgpu_profiler_bind_hwpm(struct gk20a *g, nvgpu_assert(gr_instance_id == 0U); - if (is_ctxsw) { - err = g->ops.gr.update_hwpm_ctxsw_mode(g, gr_instance_id, - tsg, 0, NVGPU_GR_CTX_HWPM_CTXSW_MODE_CTXSW); - if (err != 0) { - return err; - } - } - msg.cmd = TEGRA_VGPU_CMD_PROF_BIND_UNBIND; msg.handle = vgpu_get_handle(g); @@ -103,15 +95,6 @@ int vgpu_profiler_bind_hwpm_streamout(struct gk20a *g, nvgpu_assert(gr_instance_id == 0U); - if (is_ctxsw) { - err = g->ops.gr.update_hwpm_ctxsw_mode(g, gr_instance_id, - tsg, 0, - NVGPU_GR_CTX_HWPM_CTXSW_MODE_STREAM_OUT_CTXSW); - if (err != 0) { - return err; - } - } - msg.cmd = TEGRA_VGPU_CMD_PROF_BIND_UNBIND; msg.handle = vgpu_get_handle(g); diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c index eef9fd312..bc0352b24 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c @@ -79,7 +79,6 @@ out: int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, u32 gr_instance_id, struct nvgpu_tsg *tsg, - u64 gpu_va, u32 mode) { struct nvgpu_channel *ch; @@ -99,8 +98,7 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, nvgpu_gr_hwpm_map_get_size(gr->hwpm_map)); ret = nvgpu_gr_ctx_alloc_pm_ctx(g, gr_ctx, - gr->gr_ctx_desc, tsg->vm, - gpu_va); + gr->gr_ctx_desc, tsg->vm); if (ret != 0) { nvgpu_err(g, "failed to allocate pm ctxt buffer"); diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.h b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.h index 7ff1ef7a5..d47296227 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.h +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.h @@ -58,7 +58,7 @@ int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g, int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, u32 gr_instance_id, struct nvgpu_tsg *tsg, - u64 gpu_va, u32 mode); + u32 mode); int gr_gk20a_ctx_patch_smpc(struct gk20a *g, u32 addr, u32 data, struct nvgpu_gr_ctx *gr_ctx); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h index 80b06b2b0..887ad2d18 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h @@ -1161,7 +1161,6 @@ struct gops_gr { int (*update_hwpm_ctxsw_mode)(struct gk20a *g, u32 gr_instance_id, struct nvgpu_tsg *tsg, - u64 gpu_va, u32 mode); int (*ctx_patch_smpc)(struct gk20a *g, u32 addr, u32 data, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h b/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h index 3d535ac51..4ce054f0a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h @@ -582,8 +582,7 @@ int nvgpu_gr_ctx_zcull_setup(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, int nvgpu_gr_ctx_alloc_pm_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, struct nvgpu_gr_ctx_desc *gr_ctx_desc, - struct vm_gk20a *vm, - u64 gpu_va); + struct vm_gk20a *vm); void nvgpu_gr_ctx_free_pm_ctx(struct gk20a *g, struct vm_gk20a *vm, struct nvgpu_gr_ctx *gr_ctx); diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h index 43cc92b4f..545380e8e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h @@ -357,7 +357,6 @@ enum { }; struct tegra_vgpu_channel_set_ctxsw_mode { u32 tsg_id; - u64 gpu_va; u32 mode; }; diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index b8041d3b8..03dd8da8c 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c @@ -1175,7 +1175,7 @@ static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s, goto clean_up; } - err = g->ops.gr.update_hwpm_ctxsw_mode(g, gr_instance_id, tsg, 0, mode); + err = g->ops.gr.update_hwpm_ctxsw_mode(g, gr_instance_id, tsg, mode); if (err) nvgpu_err(g,