gpu: nvgpu: vgpu: support additional notifications

Client notification support is now added for the following:
- stalling and non-stalling GR sema release
- non-stalling FIFO channel intr
- non-stalling CE2 nonblockpipe intr

Bug 200097077

Change-Id: Icd3c076d7880e1c9ef1fcc0fc58eed9f23f39277
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/736064
(cherry picked from commit 0585d1f14d5a5ae1ccde8ccb7b7daa5593b3d1bc)
Reviewed-on: http://git-master/r/759824
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -71,6 +71,7 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
 	vgpu/ltc_vgpu.o \
 	vgpu/gr_vgpu.o \
 	vgpu/fifo_vgpu.o \
+	vgpu/ce2_vgpu.o \
 	vgpu/mm_vgpu.o \
 	vgpu/debug_vgpu.o \
 	vgpu/vgpu.o

drivers/gpu/nvgpu/vgpu/ce2_vgpu.c

@@ -0,0 +1,33 @@
+/*
+ * Virtualized GPU CE2
+ *
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "vgpu/vgpu.h"
+
+int vgpu_ce2_nonstall_isr(struct gk20a *g,
+			struct tegra_vgpu_ce2_nonstall_intr_info *info)
+{
+	gk20a_dbg_fn("");
+
+	switch (info->type) {
+	case TEGRA_VGPU_CE2_NONSTALL_INTR_NONBLOCKPIPE:
+		gk20a_channel_semaphore_wakeup(g);
+		break;
+	default:
+		WARN_ON(1);
+		break;
+	}
+
+	return 0;
+}

drivers/gpu/nvgpu/vgpu/fifo_vgpu.c

@@ -566,6 +566,23 @@ int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info)
 	return 0;
 }
 
+int vgpu_fifo_nonstall_isr(struct gk20a *g,
+			struct tegra_vgpu_fifo_nonstall_intr_info *info)
+{
+	gk20a_dbg_fn("");
+
+	switch (info->type) {
+	case TEGRA_VGPU_FIFO_NONSTALL_INTR_CHANNEL:
+		gk20a_channel_semaphore_wakeup(g);
+		break;
+	default:
+		WARN_ON(1);
+		break;
+	}
+
+	return 0;
+}
+
 void vgpu_init_fifo_ops(struct gpu_ops *gops)
 {
 	gops->fifo.bind_channel = vgpu_channel_bind;

drivers/gpu/nvgpu/vgpu/gr_vgpu.c

@@ -803,7 +803,8 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info)
 	struct channel_gk20a *ch = &f->channel[info->chid];
 
 	gk20a_dbg_fn("");
-	if (info->type != TEGRA_VGPU_GR_INTR_NOTIFY)
+	if (info->type != TEGRA_VGPU_GR_INTR_NOTIFY &&
+		info->type != TEGRA_VGPU_GR_INTR_SEMAPHORE)
 		gk20a_err(dev_from_gk20a(g), "gr intr (%d) on ch %u",
 			info->type, info->chid);
 
@@ -811,6 +812,10 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info)
 	case TEGRA_VGPU_GR_INTR_NOTIFY:
 		wake_up(&ch->notifier_wq);
 		break;
+	case TEGRA_VGPU_GR_INTR_SEMAPHORE:
+		gk20a_channel_event(ch);
+		wake_up(&ch->semaphore_wq);
+		break;
 	case TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT:
 		gk20a_set_error_notifier(ch,
 				NVGPU_CHANNEL_GR_SEMAPHORE_TIMEOUT);
@@ -846,6 +851,23 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info)
 	return 0;
 }
 
+int vgpu_gr_nonstall_isr(struct gk20a *g,
+			struct tegra_vgpu_gr_nonstall_intr_info *info)
+{
+	gk20a_dbg_fn("");
+
+	switch (info->type) {
+	case TEGRA_VGPU_GR_NONSTALL_INTR_SEMAPHORE:
+		gk20a_channel_semaphore_wakeup(g);
+		break;
+	default:
+		WARN_ON(1);
+		break;
+	}
+
+	return 0;
+}
+
 void vgpu_init_gr_ops(struct gpu_ops *gops)
 {
 	gops->gr.free_channel_ctx = vgpu_gr_free_channel_ctx;

drivers/gpu/nvgpu/vgpu/vgpu.c

@@ -114,8 +114,15 @@ static int vgpu_intr_thread(void *dev_id)
 
 		if (msg->unit == TEGRA_VGPU_INTR_GR)
 			vgpu_gr_isr(g, &msg->info.gr_intr);
+		else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_GR)
+			vgpu_gr_nonstall_isr(g, &msg->info.gr_nonstall_intr);
 		else if (msg->unit == TEGRA_VGPU_INTR_FIFO)
 			vgpu_fifo_isr(g, &msg->info.fifo_intr);
+		else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_FIFO)
+			vgpu_fifo_nonstall_isr(g,
+					&msg->info.fifo_nonstall_intr);
+		else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_CE2)
+			vgpu_ce2_nonstall_isr(g, &msg->info.ce2_nonstall_intr);
 
 		tegra_gr_comm_release(handle);
 	}

drivers/gpu/nvgpu/vgpu/vgpu.h

@@ -27,7 +27,13 @@ int vgpu_probe(struct platform_device *dev);
 int vgpu_remove(struct platform_device *dev);
 u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, u64 size);
 int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info);
+int vgpu_gr_nonstall_isr(struct gk20a *g,
+			struct tegra_vgpu_gr_nonstall_intr_info *info);
 int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info);
+int vgpu_fifo_nonstall_isr(struct gk20a *g,
+			struct tegra_vgpu_fifo_nonstall_intr_info *info);
+int vgpu_ce2_nonstall_isr(struct gk20a *g,
+			struct tegra_vgpu_ce2_nonstall_intr_info *info);
 void vgpu_init_fifo_ops(struct gpu_ops *gops);
 void vgpu_init_gr_ops(struct gpu_ops *gops);
 void vgpu_init_ltc_ops(struct gpu_ops *gops);

include/linux/tegra_vgpu.h

@@ -251,9 +251,13 @@ enum {
 	TEGRA_VGPU_GR_INTR_CLASS_ERROR,
 	TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD,
 	TEGRA_VGPU_GR_INTR_EXCEPTION,
+	TEGRA_VGPU_GR_INTR_SEMAPHORE,
 	TEGRA_VGPU_FIFO_INTR_PBDMA,
 	TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT,
-	TEGRA_VGPU_FIFO_INTR_MMU_FAULT
+	TEGRA_VGPU_FIFO_INTR_MMU_FAULT,
+	TEGRA_VGPU_GR_NONSTALL_INTR_SEMAPHORE,
+	TEGRA_VGPU_FIFO_NONSTALL_INTR_CHANNEL,
+	TEGRA_VGPU_CE2_NONSTALL_INTR_NONBLOCKPIPE
 };
 
 struct tegra_vgpu_gr_intr_info {
@@ -261,14 +265,30 @@ struct tegra_vgpu_gr_intr_info {
 	u32 chid;
 };
 
+struct tegra_vgpu_gr_nonstall_intr_info {
+	u32 type;
+};
+
 struct tegra_vgpu_fifo_intr_info {
 	u32 type;
 	u32 chid;
 };
 
+struct tegra_vgpu_fifo_nonstall_intr_info {
+	u32 type;
+};
+
+struct tegra_vgpu_ce2_nonstall_intr_info {
+	u32 type;
+};
+
 enum {
 	TEGRA_VGPU_INTR_GR = 0,
-	TEGRA_VGPU_INTR_FIFO
+	TEGRA_VGPU_INTR_FIFO,
+	TEGRA_VGPU_INTR_CE2,
+	TEGRA_VGPU_NONSTALL_INTR_GR,
+	TEGRA_VGPU_NONSTALL_INTR_FIFO,
+	TEGRA_VGPU_NONSTALL_INTR_CE2
 };
 
 enum {
@@ -281,7 +301,10 @@ struct tegra_vgpu_intr_msg {
 	u32 unit;
 	union {
 		struct tegra_vgpu_gr_intr_info gr_intr;
+		struct tegra_vgpu_gr_nonstall_intr_info gr_nonstall_intr;
 		struct tegra_vgpu_fifo_intr_info fifo_intr;
+		struct tegra_vgpu_fifo_nonstall_intr_info fifo_nonstall_intr;
+		struct tegra_vgpu_ce2_nonstall_intr_info ce2_nonstall_intr;
 	} info;
 };