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gpu: nvgpu: gm20b: Fix build warnings
Fix build warnings by removing the unused variables, functions and duplicated code. Enable -Werror to prevent new build warnings. Change-Id: Ifd73344a6e12497e6dca595ac7a6edd7ca698f88 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/497374 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit
This commit is contained in:
committed by
Dan Willemsen
parent
9981cf4424
commit
78c46b8555
@@ -1,6 +1,7 @@
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GCOV_PROFILE := y
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GCOV_PROFILE := y
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ccflags-y += -Idrivers/gpu/nvgpu
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ccflags-y += -Idrivers/gpu/nvgpu
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ccflags-y += -Wno-multichar
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ccflags-y += -Wno-multichar
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ccflags-y += -Werror
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obj-$(CONFIG_GK20A) = \
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obj-$(CONFIG_GK20A) = \
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hal_gm20b.o \
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hal_gm20b.o \
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@@ -838,8 +838,8 @@ int gm20b_bootstrap_hs_flcn(struct gk20a *g)
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int i, err = 0;
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int i, err = 0;
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struct sg_table *sgt_pmu_ucode = NULL;
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struct sg_table *sgt_pmu_ucode = NULL;
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dma_addr_t iova;
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dma_addr_t iova;
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u64 *pacr_ucode_cpuva = NULL, pacr_ucode_pmu_va, *acr_dmem;
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u64 *pacr_ucode_cpuva = NULL, pacr_ucode_pmu_va = 0, *acr_dmem;
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u32 img_size_in_bytes;
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u32 img_size_in_bytes = 0;
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u32 status, size;
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u32 status, size;
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u64 start;
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u64 start;
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struct acr_gm20b *acr = &g->acr;
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struct acr_gm20b *acr = &g->acr;
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@@ -980,9 +980,7 @@ err_release_acr_fw:
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u8 pmu_is_debug_mode_en(struct gk20a *g)
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u8 pmu_is_debug_mode_en(struct gk20a *g)
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{
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{
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int ctl_stat = gk20a_readl(g, pwr_pmu_scpctl_stat_r());
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return 1;
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return 1;
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/*TODO return (ctl_stat & pwr_pmu_scpctl_stat_debug_mode_m());*/
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}
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}
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/*
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/*
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@@ -497,7 +497,7 @@ static int gr_gm20b_ctx_state_floorsweep(struct gk20a *g)
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u32 sm_id = 0, gpc_id = 0;
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u32 sm_id = 0, gpc_id = 0;
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u32 sm_id_to_gpc_id[proj_scal_max_gpcs_v() * proj_scal_max_tpc_per_gpc_v()];
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u32 sm_id_to_gpc_id[proj_scal_max_gpcs_v() * proj_scal_max_tpc_per_gpc_v()];
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u32 tpc_per_gpc;
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u32 tpc_per_gpc;
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u32 tpc_fs_mask = 0, tpc_sm_id, gpc_tpc_id;
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u32 tpc_fs_mask = 0, tpc_sm_id = 0, gpc_tpc_id = 0;
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gk20a_dbg_fn("");
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gk20a_dbg_fn("");
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@@ -689,10 +689,6 @@ static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g)
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static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
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static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
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{
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{
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struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info;
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u64 addr_base = ucode_info->ucode_gpuva;
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int i;
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gk20a_dbg_fn("");
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gk20a_dbg_fn("");
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if (tegra_platform_is_linsim()) {
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if (tegra_platform_is_linsim()) {
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@@ -702,11 +698,7 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
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gr_gpccs_ctxsw_mailbox_value_f(0xc0de7777));
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gr_gpccs_ctxsw_mailbox_value_f(0xc0de7777));
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}
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}
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gr_gk20a_load_falcon_bind_instblk(g);
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gr_gm20b_load_gpccs_with_bootloader(g);
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g->ops.gr.falcon_load_ucode(g, addr_base,
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&g->ctxsw_ucode_info.gpccs,
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gr_gpcs_gpccs_falcon_hwcfg_r() -
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gr_fecs_falcon_hwcfg_r());
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gk20a_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), 0x0);
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gk20a_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), 0x0);
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gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(1), 0x1);
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gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(1), 0x1);
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@@ -364,4 +364,7 @@ void gm20b_init_ltc(struct gpu_ops *gops)
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gops->ltc.isr = gm20b_ltc_isr;
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gops->ltc.isr = gm20b_ltc_isr;
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gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config;
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gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config;
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gops->ltc.flush = gm20b_flush_ltc;
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gops->ltc.flush = gm20b_flush_ltc;
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#ifdef CONFIG_DEBUG_FS
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gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs;
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#endif
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}
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}
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@@ -90,52 +90,6 @@ fail:
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}
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}
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static void allocate_gmmu_pde_sparse(struct vm_gk20a *vm, u32 i)
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{
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bool small_valid, big_valid;
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u64 pte_addr[2] = {0, 0};
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struct page_table_gk20a *small_pte =
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vm->pdes.ptes[gmmu_page_size_small] + i;
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struct page_table_gk20a *big_pte =
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vm->pdes.ptes[gmmu_page_size_big] + i;
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u32 pde_v[2] = {0, 0};
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u32 *pde;
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gk20a_dbg_fn("");
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small_valid = small_pte && small_pte->ref;
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big_valid = big_pte && big_pte->ref;
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if (small_valid)
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pte_addr[gmmu_page_size_small] =
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gk20a_mm_iova_addr(small_pte->sgt->sgl);
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if (big_valid)
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pte_addr[gmmu_page_size_big] =
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gk20a_mm_iova_addr(big_pte->sgt->sgl);
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pde_v[0] = gmmu_pde_size_full_f();
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pde_v[0] |= gmmu_pde_aperture_big_invalid_f();
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pde_v[1] |= gmmu_pde_aperture_small_invalid_f() |
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gmmu_pde_vol_big_true_f();
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pde = pde_from_index(vm, i);
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gk20a_mem_wr32(pde, 0, pde_v[0]);
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gk20a_mem_wr32(pde, 1, pde_v[1]);
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smp_mb();
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FLUSH_CPU_DCACHE(pde,
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sg_phys(vm->pdes.sgt->sgl) + (i*gmmu_pde__size_v()),
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sizeof(u32)*2);
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gk20a_mm_l2_invalidate(vm->mm->g);
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gk20a_dbg(gpu_dbg_pte, "pde:%d = 0x%x,0x%08x\n", i, pde_v[1], pde_v[0]);
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vm->tlb_dirty = true;
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}
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static bool gm20b_vm_is_pde_in_range(struct vm_gk20a *vm, u64 vaddr_lo,
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static bool gm20b_vm_is_pde_in_range(struct vm_gk20a *vm, u64 vaddr_lo,
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u64 vaddr_hi, u32 pde)
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u64 vaddr_hi, u32 pde)
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{
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{
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@@ -289,10 +243,6 @@ void gm20b_vm_clear_sparse(struct vm_gk20a *vm, u64 vaddr,
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vm->mm->pde_stride_shift);
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vm->mm->pde_stride_shift);
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for (pde_i = pde_lo; pde_i <= pde_hi; pde_i++) {
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for (pde_i = pde_lo; pde_i <= pde_hi; pde_i++) {
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u32 pte_lo, pte_hi;
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u32 pte_cur;
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void *pte_kv_cur;
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struct page_table_gk20a *pte = vm->pdes.ptes[pgsz_idx] + pde_i;
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struct page_table_gk20a *pte = vm->pdes.ptes[pgsz_idx] + pde_i;
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pte->ref_cnt--;
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pte->ref_cnt--;
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