nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-23 01:50:07 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: gm20b: Fix build warnings

Browse Source 
Fix build warnings by removing the unused variables, functions and
duplicated code.

Enable -Werror to prevent new build warnings.

Change-Id: Ifd73344a6e12497e6dca595ac7a6edd7ca698f88
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/497374
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Terje Bergstrom
2014-09-10 14:32:08 +03:00
committed by Dan Willemsen
parent 9981cf4424
commit 78c46b8555
5 changed files with 8 additions and 64 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/gm20b/Makefile
View File

@@ -1,6 +1,7 @@
GCOV_PROFILE := y
ccflags-y += -Idrivers/gpu/nvgpu
ccflags-y += -Wno-multichar
ccflags-y += -Werror
obj-$(CONFIG_GK20A) = \
hal_gm20b.o \

6
drivers/gpu/nvgpu/gm20b/acr_gm20b.c
View File

@@ -838,8 +838,8 @@ int gm20b_bootstrap_hs_flcn(struct gk20a *g)
int i, err = 0;
struct sg_table *sgt_pmu_ucode = NULL;
dma_addr_t iova;
u64 *pacr_ucode_cpuva = NULL, pacr_ucode_pmu_va, *acr_dmem;
u32 img_size_in_bytes;
u64 *pacr_ucode_cpuva = NULL, pacr_ucode_pmu_va = 0, *acr_dmem;
u32 img_size_in_bytes = 0;
u32 status, size;
u64 start;
struct acr_gm20b *acr = &g->acr;
@@ -980,9 +980,7 @@ err_release_acr_fw:
u8 pmu_is_debug_mode_en(struct gk20a *g)
{
int ctl_stat = gk20a_readl(g, pwr_pmu_scpctl_stat_r());
return 1;
/*TODO return (ctl_stat & pwr_pmu_scpctl_stat_debug_mode_m());*/
}
/*

12
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -497,7 +497,7 @@ static int gr_gm20b_ctx_state_floorsweep(struct gk20a *g)
u32 sm_id = 0, gpc_id = 0;
u32 sm_id_to_gpc_id[proj_scal_max_gpcs_v() * proj_scal_max_tpc_per_gpc_v()];
u32 tpc_per_gpc;
u32 tpc_fs_mask = 0, tpc_sm_id, gpc_tpc_id;
u32 tpc_fs_mask = 0, tpc_sm_id = 0, gpc_tpc_id = 0;
gk20a_dbg_fn("");
@@ -689,10 +689,6 @@ static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g)
static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
{
struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info;
u64 addr_base = ucode_info->ucode_gpuva;
int i;
gk20a_dbg_fn("");
if (tegra_platform_is_linsim()) {
@@ -702,11 +698,7 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
gr_gpccs_ctxsw_mailbox_value_f(0xc0de7777));
}
gr_gk20a_load_falcon_bind_instblk(g);
g->ops.gr.falcon_load_ucode(g, addr_base,
&g->ctxsw_ucode_info.gpccs,
gr_gpcs_gpccs_falcon_hwcfg_r() -
gr_fecs_falcon_hwcfg_r());
gr_gm20b_load_gpccs_with_bootloader(g);
gk20a_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), 0x0);
gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(1), 0x1);

3
drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
View File

@@ -364,4 +364,7 @@ void gm20b_init_ltc(struct gpu_ops *gops)
gops->ltc.isr = gm20b_ltc_isr;
gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config;
gops->ltc.flush = gm20b_flush_ltc;
#ifdef CONFIG_DEBUG_FS
gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs;
#endif
}

50
drivers/gpu/nvgpu/gm20b/mm_gm20b.c
View File

@@ -90,52 +90,6 @@ fail:
}
static void allocate_gmmu_pde_sparse(struct vm_gk20a *vm, u32 i)
{
bool small_valid, big_valid;
u64 pte_addr[2] = {0, 0};
struct page_table_gk20a *small_pte =
vm->pdes.ptes[gmmu_page_size_small] + i;
struct page_table_gk20a *big_pte =
vm->pdes.ptes[gmmu_page_size_big] + i;
u32 pde_v[2] = {0, 0};
u32 *pde;
gk20a_dbg_fn("");
small_valid = small_pte && small_pte->ref;
big_valid = big_pte && big_pte->ref;
if (small_valid)
pte_addr[gmmu_page_size_small] =
gk20a_mm_iova_addr(small_pte->sgt->sgl);
if (big_valid)
pte_addr[gmmu_page_size_big] =
gk20a_mm_iova_addr(big_pte->sgt->sgl);
pde_v[0] = gmmu_pde_size_full_f();
pde_v[0] |= gmmu_pde_aperture_big_invalid_f();
pde_v[1] |= gmmu_pde_aperture_small_invalid_f() |
gmmu_pde_vol_big_true_f();
pde = pde_from_index(vm, i);
gk20a_mem_wr32(pde, 0, pde_v[0]);
gk20a_mem_wr32(pde, 1, pde_v[1]);
smp_mb();
FLUSH_CPU_DCACHE(pde,
sg_phys(vm->pdes.sgt->sgl) + (i*gmmu_pde__size_v()),
sizeof(u32)*2);
gk20a_mm_l2_invalidate(vm->mm->g);
gk20a_dbg(gpu_dbg_pte, "pde:%d = 0x%x,0x%08x\n", i, pde_v[1], pde_v[0]);
vm->tlb_dirty = true;
}
static bool gm20b_vm_is_pde_in_range(struct vm_gk20a *vm, u64 vaddr_lo,
u64 vaddr_hi, u32 pde)
{
@@ -289,10 +243,6 @@ void gm20b_vm_clear_sparse(struct vm_gk20a *vm, u64 vaddr,
vm->mm->pde_stride_shift);
for (pde_i = pde_lo; pde_i <= pde_hi; pde_i++) {
u32 pte_lo, pte_hi;
u32 pte_cur;
void *pte_kv_cur;
struct page_table_gk20a *pte = vm->pdes.ptes[pgsz_idx] + pde_i;
pte->ref_cnt--;