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gpu: nvgpu: remove VPR HALs from dGPUs

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gops.fb.dump_vpr_wpr_info() accesses both VPR and WPR registers.
Split this into two different HALs gops.fb.dump_vpr_info() and
gops.fb.dump_wpr_info()

Also unset HALs accessing VPR registers on dGPUs
We don't support VPR on dGPUs

Remove fb_mmu_vpr_info_r() register and all its accessors from
dGPU headers

Bug 2173122

Change-Id: I5b2712f8c5389e422a84c375a7e836add48bfd1c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1850947
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2018-09-28 14:06:15 +05:30
committed by mobile promotions
parent f22ea339b0
commit 7a033af660
14 changed files with 33 additions and 87 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/nvgpu/common/fb/fb_gm20b.c
View File

@@ -206,11 +206,11 @@ u32 gm20b_fb_compression_align_mask(struct gk20a *g)
return SZ_64K - 1;
}
void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g)
void gm20b_fb_dump_vpr_info(struct gk20a *g)
{
u32 val;
/* print vpr and wpr info */
/* print vpr info */
val = gk20a_readl(g, fb_mmu_vpr_info_r());
val &= ~0x3;
val |= fb_mmu_vpr_info_index_addr_lo_v();
@@ -220,7 +220,13 @@ void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g)
gk20a_readl(g, fb_mmu_vpr_info_r()),
gk20a_readl(g, fb_mmu_vpr_info_r()),
gk20a_readl(g, fb_mmu_vpr_info_r()));
}
void gm20b_fb_dump_wpr_info(struct gk20a *g)
{
u32 val;
/* print wpr info */
val = gk20a_readl(g, fb_mmu_wpr_info_r());
val &= ~0xf;
val |= (fb_mmu_wpr_info_index_allow_read_v());
@@ -232,7 +238,6 @@ void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g)
gk20a_readl(g, fb_mmu_wpr_info_r()),
gk20a_readl(g, fb_mmu_wpr_info_r()),
gk20a_readl(g, fb_mmu_wpr_info_r()));
}
static int gm20b_fb_vpr_info_fetch_wait(struct gk20a *g,

3
drivers/gpu/nvgpu/common/fb/fb_gm20b.h
View File

@@ -43,7 +43,8 @@ u32 gm20b_fb_mmu_debug_rd(struct gk20a *g);
unsigned int gm20b_fb_compression_page_size(struct gk20a *g);
unsigned int gm20b_fb_compressible_page_size(struct gk20a *g);
u32 gm20b_fb_compression_align_mask(struct gk20a *g);
void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g);
void gm20b_fb_dump_vpr_info(struct gk20a *g);
void gm20b_fb_dump_wpr_info(struct gk20a *g);
void gm20b_fb_read_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
int gm20b_fb_vpr_info_fetch(struct gk20a *g);
bool gm20b_fb_debug_mode_enabled(struct gk20a *g);

3
drivers/gpu/nvgpu/common/fb/fb_gv100.c
View File

@@ -141,9 +141,6 @@ int gv100_fb_memory_unlock(struct gk20a *g)
nvgpu_log_fn(g, " ");
nvgpu_log_info(g, "fb_mmu_vpr_info = 0x%08x",
gk20a_readl(g, fb_mmu_vpr_info_r()));
/*
* mem_unlock.bin should be written to install
* traps even if VPR isn’t actually supported

7
drivers/gpu/nvgpu/gk20a/mm_gk20a.c
View File

@@ -468,8 +468,11 @@ int gk20a_mm_fb_flush(struct gk20a *g)
} while (!nvgpu_timeout_expired(&timeout));
if (nvgpu_timeout_peek_expired(&timeout)) {
if (g->ops.fb.dump_vpr_wpr_info) {
g->ops.fb.dump_vpr_wpr_info(g);
if (g->ops.fb.dump_vpr_info) {
g->ops.fb.dump_vpr_info(g);
}
if (g->ops.fb.dump_wpr_info) {
g->ops.fb.dump_wpr_info(g);
}
ret = -EBUSY;
}

3
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -343,7 +343,8 @@ static const struct gpu_ops gm20b_ops = {
.compressible_page_size = gm20b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,
.vpr_info_fetch = gm20b_fb_vpr_info_fetch,
.dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
.dump_vpr_info = gm20b_fb_dump_vpr_info,
.dump_wpr_info = gm20b_fb_dump_wpr_info,
.read_wpr_info = gm20b_fb_read_wpr_info,
.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
.set_debug_mode = gm20b_fb_set_debug_mode,

5
drivers/gpu/nvgpu/gp106/hal_gp106.c
View File

@@ -418,8 +418,9 @@ static const struct gpu_ops gp106_ops = {
.compression_page_size = gp10b_fb_compression_page_size,
.compressible_page_size = gp10b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,
.vpr_info_fetch = gm20b_fb_vpr_info_fetch,
.dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
.vpr_info_fetch = NULL,
.dump_vpr_info = NULL,
.dump_wpr_info = gm20b_fb_dump_wpr_info,
.read_wpr_info = gm20b_fb_read_wpr_info,
.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
.set_debug_mode = gm20b_fb_set_debug_mode,

3
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -380,7 +380,8 @@ static const struct gpu_ops gp10b_ops = {
.compressible_page_size = gp10b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,
.vpr_info_fetch = gm20b_fb_vpr_info_fetch,
.dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
.dump_vpr_info = gm20b_fb_dump_vpr_info,
.dump_wpr_info = gm20b_fb_dump_wpr_info,
.read_wpr_info = gm20b_fb_read_wpr_info,
.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
.set_debug_mode = gm20b_fb_set_debug_mode,

5
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -480,8 +480,9 @@ static const struct gpu_ops gv100_ops = {
.compression_page_size = gp10b_fb_compression_page_size,
.compressible_page_size = gp10b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,
.vpr_info_fetch = gm20b_fb_vpr_info_fetch,
.dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
.vpr_info_fetch = NULL,
.dump_vpr_info = NULL,
.dump_wpr_info = gm20b_fb_dump_wpr_info,
.read_wpr_info = gm20b_fb_read_wpr_info,
.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
.set_debug_mode = gm20b_fb_set_debug_mode,

3
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -444,7 +444,8 @@ static const struct gpu_ops gv11b_ops = {
.compressible_page_size = gp10b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,
.vpr_info_fetch = gm20b_fb_vpr_info_fetch,
.dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
.dump_vpr_info = gm20b_fb_dump_vpr_info,
.dump_wpr_info = gm20b_fb_dump_wpr_info,
.read_wpr_info = gm20b_fb_read_wpr_info,
.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
.set_debug_mode = gm20b_fb_set_debug_mode,

3
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -549,7 +549,8 @@ struct gpu_ops {
*/
u32 (*compression_align_mask)(struct gk20a *g);
void (*dump_vpr_wpr_info)(struct gk20a *g);
void (*dump_vpr_info)(struct gk20a *g);
void (*dump_wpr_info)(struct gk20a *g);
int (*vpr_info_fetch)(struct gk20a *g);
void (*read_wpr_info)(struct gk20a *g,
struct wpr_carveout_info *inf);

16
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h
View File

@@ -448,22 +448,6 @@ static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_vpr_info_r(void)
{
return 0x00100cd0U;
}
static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
{
return 0x00000000U;
}
static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
{
return 0x00000001U;
}
static inline u32 fb_mmu_priv_level_mask_r(void)
{
return 0x00100cdcU;

52
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h
View File

@@ -680,58 +680,6 @@ static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 fb_mmu_vpr_info_r(void)
{
return 0x00100cd0U;
}
static inline u32 fb_mmu_vpr_info_index_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 fb_mmu_vpr_info_index_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 fb_mmu_vpr_info_index_m(void)
{
return 0x3U << 0U;
}
static inline u32 fb_mmu_vpr_info_index_addr_lo_v(void)
{
return 0x00000000U;
}
static inline u32 fb_mmu_vpr_info_index_addr_hi_v(void)
{
return 0x00000001U;
}
static inline u32 fb_mmu_vpr_info_index_cya_lo_v(void)
{
return 0x00000002U;
}
static inline u32 fb_mmu_vpr_info_index_cya_hi_v(void)
{
return 0x00000003U;
}
static inline u32 fb_mmu_vpr_info_cya_lo_in_use_m(void)
{
return 0x1U << 4U;
}
static inline u32 fb_mmu_vpr_info_fetch_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
{
return 0x00000000U;
}
static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
{
return 0x00000001U;
}
static inline u32 fb_niso_cfg1_r(void)
{
return 0x00100c14U;

3
drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -244,7 +244,8 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.compressible_page_size = gp10b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,
.vpr_info_fetch = NULL,
.dump_vpr_wpr_info = NULL,
.dump_vpr_info = NULL,
.dump_wpr_info = NULL,
.read_wpr_info = NULL,
.is_debug_mode_enabled = NULL,
.set_debug_mode = vgpu_mm_mmu_set_debug_mode,

3
drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -285,7 +285,8 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.compressible_page_size = gp10b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,
.vpr_info_fetch = NULL,
.dump_vpr_wpr_info = NULL,
.dump_vpr_info = NULL,
.dump_wpr_info = NULL,
.read_wpr_info = NULL,
.is_debug_mode_enabled = NULL,
.set_debug_mode = vgpu_mm_mmu_set_debug_mode,