gpu: nvgpu: Fix Gpu sysfs access to Fmax@Vmin

Currently gpu sysfs retrieves Fmax@Vmin by direct call into Tegra DVFS
driver that introduces compile time dependencies on CONFIG_TEGRA_DVFS.
In addition incorrect clock is used for DVFS information access.

Re-factored sysfs node to use generic GPU clock operation for Fmax@Vmin
read. This would fix a bug in target clock selection, and allows to
remove dependency of sysfs on CONFIG_TEGRA_DVFS.

Updated nvgpu_linux_get_fmax_at_vmin_safe operation itself so it can be
called on platforms that does not support Tegra DVFS, although 0 will
still be returned as Fmax@Vmin on such platforms.

Bug 2045903

Change-Id: I32cce25320df026288c82458c913b0cde9ad4f72
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1710924
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Frid
2018-05-08 18:58:22 -07:00
committed by mobile promotions
parent 0732f4b83e
commit 7a28547892
4 changed files with 17 additions and 19 deletions

View File

@@ -84,15 +84,18 @@ static int nvgpu_linux_clk_set_rate(struct gk20a *g,
return ret;
}
static unsigned long nvgpu_linux_get_fmax_at_vmin_safe(struct clk_gk20a *clk)
static unsigned long nvgpu_linux_get_fmax_at_vmin_safe(struct gk20a *g)
{
/*
* On Tegra GPU clock exposed to frequency governor is a shared user on
* GPCPLL bus (gbus). The latter can be accessed as GPU clock parent.
* Respectively the grandparent is PLL reference clock.
* On Tegra platforms with GPCPLL bus (gbus) GPU tegra_clk clock exposed
* to frequency governor is a shared user on the gbus. The latter can be
* accessed as GPU clock parent, and incorporate DVFS related data.
*/
return tegra_dvfs_get_fmax_at_vmin_safe_t(
clk_get_parent(clk->tegra_clk));
if (g->clk.tegra_clk)
return tegra_dvfs_get_fmax_at_vmin_safe_t(
clk_get_parent(g->clk.tegra_clk));
return 0;
}
static u32 nvgpu_linux_get_ref_clock_rate(struct gk20a *g)