gpu: nvgpu: add hal for pmu sequence cleanup

- On older chips, PMU uses CMD-MSG queue method to
  communicate with NvGPU.
- From Turing onwards, PMU uses RPC method for this.
- During poweroff, we release pmu_sequence and reset the
  members of the structure.
- For chips that use RPC, we need to free the payload as well
  and then reset the members.
- Add pmu_seq_cleanup hal for this.

Bug 4019694
Bug 4059157

Change-Id: Ieb474fe4ed81f54d78480214cde53b51d45652c6
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2882267
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/pmu/ipc/pmu_seq.c

@@ -20,6 +20,7 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
+#include <nvgpu/gk20a.h>
 #include <nvgpu/pmu/seq.h>
 #include <nvgpu/bitops.h>
 #include <nvgpu/errno.h>
@@ -91,7 +92,7 @@ void nvgpu_pmu_sequences_cleanup(struct gk20a *g, struct nvgpu_pmu *pmu,
 
 	for (i = 0; i < PMU_MAX_NUM_SEQUENCES; i++) {
 		if (sequences->seq[i].cb_params != NULL) {
-			nvgpu_pmu_seq_free_release(g, sequences,
+			 g->ops.pmu.pmu_seq_cleanup(g, sequences,
 						&sequences->seq[i]);
 			nvgpu_pmu_dbg(g, "sequences cleanup done");
 		}

drivers/gpu/nvgpu/hal/init/hal_ga100.c

@@ -30,6 +30,7 @@
 #include <nvgpu/pmu.h>
 #ifdef CONFIG_NVGPU_LS_PMU
 #include <nvgpu/pmu/pmu_pstate.h>
+#include <nvgpu/pmu/seq.h>
 #endif
 #include <nvgpu/therm.h>
 #include <nvgpu/clk_arb.h>
@@ -1382,6 +1383,7 @@ static const struct gops_pmu ga100_ops_pmu = {
 	.setup_apertures = tu104_pmu_setup_apertures,
 	.secured_pmu_start = gm20b_secured_pmu_start,
 	.pmu_clear_bar0_host_err_status = gm20b_clear_pmu_bar0_host_err_status,
+	.pmu_seq_cleanup = nvgpu_pmu_seq_free_release,
 };
 #endif
 

drivers/gpu/nvgpu/hal/init/hal_ga10b.c

@@ -31,6 +31,7 @@
 #include <nvgpu/pmu.h>
 #ifdef CONFIG_NVGPU_LS_PMU
 #include <nvgpu/pmu/pmu_pstate.h>
+#include <nvgpu/pmu/seq.h>
 #endif
 #include <nvgpu/therm.h>
 #include <nvgpu/clk_arb.h>
@@ -1407,6 +1408,7 @@ static const struct gops_pmu ga10b_ops_pmu = {
 	.pmu_isr = gk20a_pmu_isr,
 	.handle_ext_irq = ga10b_pmu_handle_ext_irq,
 #ifdef CONFIG_NVGPU_LS_PMU
+	.pmu_seq_cleanup = nvgpu_pmu_seq_free_release,
 	.get_inst_block_config = ga10b_pmu_get_inst_block_config,
 	/* Init */
 	.pmu_rtos_init = nvgpu_pmu_rtos_init,

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -53,6 +53,7 @@
 #include <nvgpu/pmu.h>
 #ifdef CONFIG_NVGPU_LS_PMU
 #include <nvgpu/pmu/pmu_pstate.h>
+#include <nvgpu/pmu/seq.h>
 #endif
 #include <nvgpu/therm.h>
 #ifdef CONFIG_NVGPU_CLK_ARB
@@ -876,6 +877,7 @@ static const struct gops_pmu gm20b_ops_pmu = {
 	.setup_apertures = gm20b_pmu_setup_apertures,
 	.secured_pmu_start = gm20b_secured_pmu_start,
 	.handle_swgen1_irq = NULL,
+	.pmu_seq_cleanup = nvgpu_pmu_seq_release,
 };
 #endif
 

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -29,6 +29,7 @@
 #include <nvgpu/pmu.h>
 #ifdef CONFIG_NVGPU_LS_PMU
 #include <nvgpu/pmu/pmu_pstate.h>
+#include <nvgpu/pmu/seq.h>
 #endif
 #include <nvgpu/therm.h>
 #ifdef CONFIG_NVGPU_CLK_ARB
@@ -1191,6 +1192,8 @@ static const struct gops_pmu gv11b_ops_pmu = {
 	.pmu_queue_head = gk20a_pmu_queue_head,
 	.pmu_queue_tail = gk20a_pmu_queue_tail,
 	.pmu_msgq_tail = gk20a_pmu_msgq_tail,
+	/* pmu sequence */
+	.pmu_seq_cleanup = nvgpu_pmu_seq_release,
 	/* mutex */
 	.pmu_mutex_size = gv11b_pmu_mutex__size_1_v,
 	.pmu_mutex_owner = gk20a_pmu_mutex_owner,

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -223,6 +223,7 @@
 #include <nvgpu/nvenc.h>
 #ifdef CONFIG_NVGPU_LS_PMU
 #include <nvgpu/pmu/pmu_pstate.h>
+#include <nvgpu/pmu/seq.h>
 #endif
 #include <nvgpu/therm.h>
 #include <nvgpu/clk_arb.h>
@@ -1266,6 +1267,7 @@ static const struct gops_pmu tu104_ops_pmu = {
 	.setup_apertures = tu104_pmu_setup_apertures,
 	.secured_pmu_start = gm20b_secured_pmu_start,
 	.pmu_clear_bar0_host_err_status = gm20b_clear_pmu_bar0_host_err_status,
+	.pmu_seq_cleanup = nvgpu_pmu_seq_free_release,
 };
 #endif
 

drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h

@@ -304,6 +304,9 @@ struct gops_pmu {
 	int (*pmu_destroy)(struct gk20a *g, struct nvgpu_pmu *pmu);
 	int (*pmu_pstate_sw_setup)(struct gk20a *g);
 	int (*pmu_pstate_pmu_setup)(struct gk20a *g);
+	void (*pmu_seq_cleanup)(struct gk20a *g,
+			struct pmu_sequences *sequences,
+			struct pmu_sequence *seq);
 #endif
 
 	struct nvgpu_hw_err_inject_info_desc * (*get_pmu_err_desc)