diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
index f9d452569..75301486e 100644
--- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -671,7 +671,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 	.mc = {
 		.intr_mask = NULL,
 		.intr_enable = NULL,
-		.intr_unit_config = NULL,
+		.intr_pmu_unit_config = NULL,
 		.isr_stall = NULL,
 		.intr_stall = NULL,
 		.intr_stall_pause = NULL,
diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
index 872d25d46..a0cf26102 100644
--- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -761,7 +761,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 	.mc = {
 		.intr_mask = NULL,
 		.intr_enable = NULL,
-		.intr_unit_config = NULL,
+		.intr_pmu_unit_config = NULL,
 		.isr_stall = NULL,
 		.intr_stall = NULL,
 		.intr_stall_pause = NULL,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
index 1f2140265..e1f845b61 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
@@ -841,7 +841,7 @@ static const struct gpu_ops gm20b_ops = {
 	.mc = {
 		.intr_mask = gm20b_mc_intr_mask,
 		.intr_enable = gm20b_mc_intr_enable,
-		.intr_unit_config = gm20b_mc_intr_unit_config,
+		.intr_pmu_unit_config = gm20b_mc_intr_pmu_unit_config,
 		.isr_stall = gm20b_mc_isr_stall,
 		.intr_stall = gm20b_mc_intr_stall,
 		.intr_stall_pause = gm20b_mc_intr_stall_pause,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
index 27499aeb4..29b40b097 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
@@ -922,7 +922,7 @@ static const struct gpu_ops gp10b_ops = {
 	.mc = {
 		.intr_mask = mc_gp10b_intr_mask,
 		.intr_enable = mc_gp10b_intr_enable,
-		.intr_unit_config = mc_gp10b_intr_unit_config,
+		.intr_pmu_unit_config = mc_gp10b_intr_pmu_unit_config,
 		.isr_stall = mc_gp10b_isr_stall,
 		.intr_stall = mc_gp10b_intr_stall,
 		.intr_stall_pause = mc_gp10b_intr_stall_pause,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
index 1eada43b9..aa84bc9a8 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
@@ -1077,7 +1077,7 @@ static const struct gpu_ops gv11b_ops = {
 	.mc = {
 		.intr_mask = mc_gp10b_intr_mask,
 		.intr_enable = mc_gv11b_intr_enable,
-		.intr_unit_config = mc_gp10b_intr_unit_config,
+		.intr_pmu_unit_config = mc_gp10b_intr_pmu_unit_config,
 		.isr_stall = mc_gp10b_isr_stall,
 		.intr_stall = mc_gp10b_intr_stall,
 		.intr_stall_pause = mc_gp10b_intr_stall_pause,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
index 6a24361e0..3feb39301 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -1130,7 +1130,7 @@ static const struct gpu_ops tu104_ops = {
 	.mc = {
 		.intr_enable = intr_tu104_enable,
 		.intr_mask = intr_tu104_mask,
-		.intr_unit_config = mc_gp10b_intr_unit_config,
+		.intr_pmu_unit_config = mc_gp10b_intr_pmu_unit_config,
 		.isr_stall = mc_gp10b_isr_stall,
 		.intr_stall = intr_tu104_stall,
 		.intr_stall_pause = intr_tu104_stall_pause,
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c
index b2351d4a8..5450ebec8 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c
@@ -156,20 +156,19 @@ void gm20b_mc_intr_enable(struct gk20a *g)
 		mc_intr_en_0_inta_hardware_f());
 }
 
-void gm20b_mc_intr_unit_config(struct gk20a *g, bool enable,
-		bool is_stalling, u32 mask)
+void gm20b_mc_intr_pmu_unit_config(struct gk20a *g, bool enable)
 {
-	u32 mask_reg = (is_stalling ? mc_intr_mask_0_r() :
-					mc_intr_mask_1_r());
-
 	if (enable) {
-		nvgpu_writel(g, mask_reg,
-			nvgpu_readl(g, mask_reg) |
-			mask);
+		nvgpu_writel(g, mc_intr_mask_0_r(),
+			nvgpu_readl(g, mc_intr_mask_0_r()) |
+			mc_intr_mask_0_pmu_enabled_f());
 	} else {
-		nvgpu_writel(g, mask_reg,
-			nvgpu_readl(g, mask_reg) &
-			~mask);
+		nvgpu_writel(g, mc_intr_mask_0_r(),
+			nvgpu_readl(g, mc_intr_mask_0_r()) &
+			~mc_intr_mask_0_pmu_enabled_f());
+		nvgpu_writel(g, mc_intr_mask_1_r(),
+			nvgpu_readl(g, mc_intr_mask_1_r()) &
+			~mc_intr_mask_1_pmu_enabled_f());
 	}
 }
 
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.h b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.h
index 54d4b4cc0..7d9a9b378 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.h
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.h
@@ -34,8 +34,7 @@ enum nvgpu_unit;
 
 void gm20b_mc_intr_mask(struct gk20a *g);
 void gm20b_mc_intr_enable(struct gk20a *g);
-void gm20b_mc_intr_unit_config(struct gk20a *g, bool enable,
-		bool is_stalling, u32 mask);
+void gm20b_mc_intr_pmu_unit_config(struct gk20a *g, bool enable);
 void gm20b_mc_isr_stall(struct gk20a *g);
 u32  gm20b_mc_intr_stall(struct gk20a *g);
 void gm20b_mc_intr_stall_pause(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.c b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.c
index 99cfe997b..32786e646 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.c
@@ -70,24 +70,27 @@ void mc_gp10b_intr_enable(struct gk20a *g)
 			g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
 }
 
-void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
-		bool is_stalling, u32 mask)
+void mc_gp10b_intr_pmu_unit_config(struct gk20a *g, bool enable)
 {
-	u32 intr_index = 0U;
 	u32 reg = 0U;
 
-	intr_index = (is_stalling ? NVGPU_MC_INTR_STALLING :
-			NVGPU_MC_INTR_NONSTALLING);
 	if (enable) {
-		reg = mc_intr_en_set_r(intr_index);
-		g->mc_intr_mask_restore[intr_index] |= mask;
+		reg = mc_intr_en_set_r(NVGPU_MC_INTR_STALLING);
+		g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] |=
+			mc_intr_pmu_pending_f();
+		nvgpu_writel(g, reg, mc_intr_pmu_pending_f());
 
 	} else {
-		reg = mc_intr_en_clear_r(intr_index);
-		g->mc_intr_mask_restore[intr_index] &= ~mask;
-	}
+		reg = mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING);
+		g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] &=
+			~mc_intr_pmu_pending_f();
+		nvgpu_writel(g, reg, mc_intr_pmu_pending_f());
 
-	nvgpu_writel(g, reg, mask);
+		reg = mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING);
+		g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] &=
+			~mc_intr_pmu_pending_f();
+		nvgpu_writel(g, reg, mc_intr_pmu_pending_f());
+	}
 }
 
 void mc_gp10b_isr_stall(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h
index 70c0cfbef..c9cbd6f89 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h
@@ -32,8 +32,7 @@ enum nvgpu_unit;
 
 void mc_gp10b_intr_mask(struct gk20a *g);
 void mc_gp10b_intr_enable(struct gk20a *g);
-void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
-		bool is_stalling, u32 mask);
+void mc_gp10b_intr_pmu_unit_config(struct gk20a *g, bool enable);
 void mc_gp10b_isr_stall(struct gk20a *g);
 bool mc_gp10b_is_intr1_pending(struct gk20a *g,
 				      enum nvgpu_unit unit, u32 mc_intr_1);
diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c
index 9627b4ce5..8f6039a07 100644
--- a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c
@@ -32,7 +32,6 @@
 #include <nvgpu/pmu/pmu_pg.h>
 
 #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 
 #include "pmu_gk20a.h"
 
@@ -445,10 +444,7 @@ void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable)
 
 	nvgpu_log_fn(g, " ");
 
-	g->ops.mc.intr_unit_config(g, MC_INTR_UNIT_DISABLE, true,
-			mc_intr_mask_0_pmu_enabled_f());
-	g->ops.mc.intr_unit_config(g, MC_INTR_UNIT_DISABLE, false,
-			mc_intr_mask_1_pmu_enabled_f());
+	g->ops.mc.intr_pmu_unit_config(g, MC_INTR_UNIT_DISABLE);
 
 	nvgpu_falcon_set_irq(pmu->flcn, false, 0x0, 0x0);
 
@@ -466,8 +462,7 @@ void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable)
 
 		nvgpu_falcon_set_irq(pmu->flcn, true, intr_mask, intr_dest);
 
-		g->ops.mc.intr_unit_config(g, MC_INTR_UNIT_ENABLE, true,
-				mc_intr_mask_0_pmu_enabled_f());
+		g->ops.mc.intr_pmu_unit_config(g, MC_INTR_UNIT_ENABLE);
 	}
 
 	nvgpu_log_fn(g, "done");
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 0622274da..5b32211be 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -1463,8 +1463,8 @@ struct gpu_ops {
 	struct {
 		void (*intr_mask)(struct gk20a *g);
 		void (*intr_enable)(struct gk20a *g);
-		void (*intr_unit_config)(struct gk20a *g,
-				bool enable, bool is_stalling, u32 mask);
+		void (*intr_pmu_unit_config)(struct gk20a *g,
+				bool enable);
 		void (*isr_stall)(struct gk20a *g);
 		bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr);
 		bool (*is_intr_nvlink_pending)(struct gk20a *g, u32 mc_intr);