diff --git a/arch/nvgpu-common.yaml b/arch/nvgpu-common.yaml index 2050c882b..bc45a4185 100644 --- a/arch/nvgpu-common.yaml +++ b/arch/nvgpu-common.yaml @@ -92,7 +92,12 @@ fence: safe: no owner: Seema K sources: [ common/fence/fence.c, + common/fence/fence_syncpt.c, + common/fence/fence_sema.c, + common/fence/fence_priv.h, include/nvgpu/fence.h, + include/nvgpu/fence_syncpt.h, + include/nvgpu/fence_sema.h, include/nvgpu/user_fence.h ] io: diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 616197107..5dea67664 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -462,7 +462,8 @@ nvgpu-$(CONFIG_NVGPU_SYNCFD_STABLE) += \ os/linux/os_fence_dma_sema.o nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += \ - common/sync/channel_sync_syncpt.o + common/sync/channel_sync_syncpt.o \ + common/fence/fence_syncpt.o ifneq ($(CONFIG_NVGPU_SYNCFD_NONE),y) nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += \ os/linux/os_fence_syncpt.o @@ -546,6 +547,7 @@ nvgpu-y += \ common/fifo/userd.o \ common/fifo/watchdog.o \ common/fence/fence.o \ + common/fence/fence_sema.o \ common/ecc.o \ common/log_common.o \ common/ce/ce.o \ diff --git a/drivers/gpu/nvgpu/Makefile.shared.configs b/drivers/gpu/nvgpu/Makefile.shared.configs index 222f939bc..1912a7f58 100644 --- a/drivers/gpu/nvgpu/Makefile.shared.configs +++ b/drivers/gpu/nvgpu/Makefile.shared.configs @@ -53,7 +53,6 @@ NVGPU_COMMON_CFLAGS := # NVGPU_COMMON_CFLAGS += \ - -DCONFIG_TEGRA_GK20A_NVHOST \ -DCONFIG_NVGPU_SUPPORT_TURING \ -DCONFIG_TEGRA_GK20A_PMU=1 \ -DCONFIG_TEGRA_ACR=1 \ @@ -63,7 +62,12 @@ NVGPU_COMMON_CFLAGS += \ CONFIG_NVGPU_LOGGING := 1 NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_LOGGING -CONFIG_NVGPU_SYNCFD_NONE := 1 +# Syncpoint support provided by nvhost is expected to exist. +CONFIG_TEGRA_GK20A_NVHOST := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_TEGRA_GK20A_NVHOST + +# Syncfds are a Linux feature. +CONFIG_NVGPU_SYNCFD_NONE := 1 NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_SYNCFD_NONE ifeq ($(profile),$(filter $(profile),safety_debug safety_release)) diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index ba8221635..d5df951ed 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -428,6 +428,12 @@ endif ifeq ($(CONFIG_NVGPU_FENCE),1) srcs += common/fence/fence.c +ifeq ($(CONFIG_TEGRA_GK20A_NVHOST),1) +srcs += common/fence/fence_syncpt.c +endif +ifeq ($(CONFIG_NVGPU_SW_SEMAPHORE),1) +srcs += common/fence/fence_sema.c +endif endif ifeq ($(CONFIG_NVGPU_FECS_TRACE),1) diff --git a/drivers/gpu/nvgpu/common/fence/fence.c b/drivers/gpu/nvgpu/common/fence/fence.c index fa1c1c96b..608f29b22 100644 --- a/drivers/gpu/nvgpu/common/fence/fence.c +++ b/drivers/gpu/nvgpu/common/fence/fence.c @@ -20,17 +20,12 @@ * DEALINGS IN THE SOFTWARE. */ -#include #include -#include -#include #include #include -#include -#include #include -#include #include +#include "fence_priv.h" static struct nvgpu_fence_type *nvgpu_fence_from_ref(struct nvgpu_ref *ref) { @@ -46,11 +41,7 @@ static void nvgpu_fence_free(struct nvgpu_ref *ref) f->os_fence.ops->drop_ref(&f->os_fence); } -#ifdef CONFIG_NVGPU_SW_SEMAPHORE - if (f->semaphore != NULL) { - nvgpu_semaphore_put(f->semaphore); - } -#endif + f->ops->free(f); } void nvgpu_fence_put(struct nvgpu_fence_type *f) @@ -71,8 +62,10 @@ struct nvgpu_fence_type *nvgpu_fence_get(struct nvgpu_fence_type *f) struct nvgpu_user_fence nvgpu_fence_extract_user(struct nvgpu_fence_type *f) { struct nvgpu_user_fence uf = (struct nvgpu_user_fence) { +#ifdef CONFIG_TEGRA_GK20A_NVHOST .syncpt_id = f->syncpt_id, .syncpt_value = f->syncpt_value, +#endif .os_fence = f->os_fence, }; @@ -110,101 +103,5 @@ void nvgpu_fence_init(struct nvgpu_fence_type *f, { nvgpu_ref_init(&f->ref); f->ops = ops; - f->syncpt_id = NVGPU_INVALID_SYNCPT_ID; -#ifdef CONFIG_NVGPU_SW_SEMAPHORE - f->semaphore = NULL; -#endif f->os_fence = os_fence; } - -#ifdef CONFIG_NVGPU_SW_SEMAPHORE -/* Fences that are backed by GPU semaphores: */ - -static int nvgpu_semaphore_fence_wait(struct nvgpu_fence_type *f, u32 timeout) -{ - if (!nvgpu_semaphore_is_acquired(f->semaphore)) { - return 0; - } - - return NVGPU_COND_WAIT_INTERRUPTIBLE( - f->semaphore_wq, - !nvgpu_semaphore_is_acquired(f->semaphore), - timeout); -} - -static bool nvgpu_semaphore_fence_is_expired(struct nvgpu_fence_type *f) -{ - return !nvgpu_semaphore_is_acquired(f->semaphore); -} - -static const struct nvgpu_fence_ops nvgpu_semaphore_fence_ops = { - .wait = &nvgpu_semaphore_fence_wait, - .is_expired = &nvgpu_semaphore_fence_is_expired, -}; - -/* This function takes ownership of the semaphore as well as the os_fence */ -void nvgpu_fence_from_semaphore( - struct nvgpu_fence_type *f, - struct nvgpu_semaphore *semaphore, - struct nvgpu_cond *semaphore_wq, - struct nvgpu_os_fence os_fence) -{ - nvgpu_fence_init(f, &nvgpu_semaphore_fence_ops, os_fence); - - f->semaphore = semaphore; - f->semaphore_wq = semaphore_wq; -} - -#endif - -#ifdef CONFIG_TEGRA_GK20A_NVHOST -/* Fences that are backed by host1x syncpoints: */ - -static int nvgpu_fence_syncpt_wait(struct nvgpu_fence_type *f, u32 timeout) -{ - return nvgpu_nvhost_syncpt_wait_timeout_ext( - f->nvhost_dev, f->syncpt_id, f->syncpt_value, - timeout, NVGPU_NVHOST_DEFAULT_WAITER); -} - -static bool nvgpu_fence_syncpt_is_expired(struct nvgpu_fence_type *f) -{ - - /* - * In cases we don't register a notifier, we can't expect the - * syncpt value to be updated. For this case, we force a read - * of the value from HW, and then check for expiration. - */ - if (!nvgpu_nvhost_syncpt_is_expired_ext(f->nvhost_dev, f->syncpt_id, - f->syncpt_value)) { - u32 val; - - if (!nvgpu_nvhost_syncpt_read_ext_check(f->nvhost_dev, - f->syncpt_id, &val)) { - return nvgpu_nvhost_syncpt_is_expired_ext( - f->nvhost_dev, - f->syncpt_id, f->syncpt_value); - } - } - - return true; -} - -static const struct nvgpu_fence_ops nvgpu_fence_syncpt_ops = { - .wait = &nvgpu_fence_syncpt_wait, - .is_expired = &nvgpu_fence_syncpt_is_expired, -}; - -/* This function takes the ownership of the os_fence */ -void nvgpu_fence_from_syncpt( - struct nvgpu_fence_type *f, - struct nvgpu_nvhost_dev *nvhost_dev, - u32 id, u32 value, struct nvgpu_os_fence os_fence) -{ - nvgpu_fence_init(f, &nvgpu_fence_syncpt_ops, os_fence); - - f->nvhost_dev = nvhost_dev; - f->syncpt_id = id; - f->syncpt_value = value; -} -#endif diff --git a/drivers/gpu/nvgpu/common/fence/fence_priv.h b/drivers/gpu/nvgpu/common/fence/fence_priv.h new file mode 100644 index 000000000..14e45d1ed --- /dev/null +++ b/drivers/gpu/nvgpu/common/fence/fence_priv.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_FENCE_PRIV_H +#define NVGPU_FENCE_PRIV_H + +#include + +struct nvgpu_fence_type; + +struct nvgpu_fence_ops { + int (*wait)(struct nvgpu_fence_type *f, u32 timeout); + bool (*is_expired)(struct nvgpu_fence_type *f); + void (*free)(struct nvgpu_fence_type *f); +}; + +void nvgpu_fence_init(struct nvgpu_fence_type *f, + const struct nvgpu_fence_ops *ops, + struct nvgpu_os_fence os_fence); + +#endif diff --git a/drivers/gpu/nvgpu/common/fence/fence_sema.c b/drivers/gpu/nvgpu/common/fence/fence_sema.c new file mode 100644 index 000000000..521076a04 --- /dev/null +++ b/drivers/gpu/nvgpu/common/fence/fence_sema.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include "fence_priv.h" + +static int nvgpu_fence_semaphore_wait(struct nvgpu_fence_type *f, u32 timeout) +{ + if (!nvgpu_semaphore_is_acquired(f->semaphore)) { + return 0; + } + + return NVGPU_COND_WAIT_INTERRUPTIBLE( + f->semaphore_wq, + !nvgpu_semaphore_is_acquired(f->semaphore), + timeout); +} + +static bool nvgpu_fence_semaphore_is_expired(struct nvgpu_fence_type *f) +{ + return !nvgpu_semaphore_is_acquired(f->semaphore); +} + +static void nvgpu_fence_semaphore_free(struct nvgpu_fence_type *f) +{ + if (f->semaphore != NULL) { + nvgpu_semaphore_put(f->semaphore); + } +} + +static const struct nvgpu_fence_ops nvgpu_fence_semaphore_ops = { + .wait = nvgpu_fence_semaphore_wait, + .is_expired = nvgpu_fence_semaphore_is_expired, + .free = nvgpu_fence_semaphore_free, +}; + +/* This function takes ownership of the semaphore as well as the os_fence */ +void nvgpu_fence_from_semaphore( + struct nvgpu_fence_type *f, + struct nvgpu_semaphore *semaphore, + struct nvgpu_cond *semaphore_wq, + struct nvgpu_os_fence os_fence) +{ + nvgpu_fence_init(f, &nvgpu_fence_semaphore_ops, os_fence); + + f->semaphore = semaphore; + f->semaphore_wq = semaphore_wq; +} diff --git a/drivers/gpu/nvgpu/common/fence/fence_syncpt.c b/drivers/gpu/nvgpu/common/fence/fence_syncpt.c new file mode 100644 index 000000000..015cfc7f1 --- /dev/null +++ b/drivers/gpu/nvgpu/common/fence/fence_syncpt.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include "fence_priv.h" + +static int nvgpu_fence_syncpt_wait(struct nvgpu_fence_type *f, u32 timeout) +{ + return nvgpu_nvhost_syncpt_wait_timeout_ext( + f->nvhost_dev, f->syncpt_id, f->syncpt_value, + timeout, NVGPU_NVHOST_DEFAULT_WAITER); +} + +static bool nvgpu_fence_syncpt_is_expired(struct nvgpu_fence_type *f) +{ + /* + * In cases we don't register a notifier, we can't expect the + * syncpt value to be updated. For this case, we force a read + * of the value from HW, and then check for expiration. + */ + if (!nvgpu_nvhost_syncpt_is_expired_ext(f->nvhost_dev, f->syncpt_id, + f->syncpt_value)) { + u32 val; + + if (!nvgpu_nvhost_syncpt_read_ext_check(f->nvhost_dev, + f->syncpt_id, &val)) { + return nvgpu_nvhost_syncpt_is_expired_ext( + f->nvhost_dev, + f->syncpt_id, f->syncpt_value); + } + } + + return true; +} + +static void nvgpu_fence_syncpt_free(struct nvgpu_fence_type *f) +{ +} + +static const struct nvgpu_fence_ops nvgpu_fence_syncpt_ops = { + .wait = nvgpu_fence_syncpt_wait, + .is_expired = nvgpu_fence_syncpt_is_expired, + .free = nvgpu_fence_syncpt_free, +}; + +/* This function takes the ownership of the os_fence */ +void nvgpu_fence_from_syncpt( + struct nvgpu_fence_type *f, + struct nvgpu_nvhost_dev *nvhost_dev, + u32 id, u32 value, struct nvgpu_os_fence os_fence) +{ + nvgpu_fence_init(f, &nvgpu_fence_syncpt_ops, os_fence); + + f->nvhost_dev = nvhost_dev; + f->syncpt_id = id; + f->syncpt_value = value; +} diff --git a/drivers/gpu/nvgpu/common/fifo/submit.c b/drivers/gpu/nvgpu/common/fifo/submit.c index ea722aac3..9f17f5f8c 100644 --- a/drivers/gpu/nvgpu/common/fifo/submit.c +++ b/drivers/gpu/nvgpu/common/fifo/submit.c @@ -773,10 +773,16 @@ static int nvgpu_submit_channel_gpfifo(struct nvgpu_channel *c, #ifdef CONFIG_NVGPU_TRACE if (fence_out != NULL && *fence_out != NULL) { +#ifdef CONFIG_TEGRA_GK20A_NVHOST trace_gk20a_channel_submitted_gpfifo(g->name, c->chid, num_entries, flags, (*fence_out)->syncpt_id, (*fence_out)->syncpt_value); +#else + trace_gk20a_channel_submitted_gpfifo(g->name, + c->chid, num_entries, flags, + 0, 0); +#endif } else { trace_gk20a_channel_submitted_gpfifo(g->name, c->chid, num_entries, flags, diff --git a/drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c b/drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c index c7e640eae..4233d4507 100644 --- a/drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c +++ b/drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c @@ -37,6 +37,7 @@ #include #include #include +#include #include "channel_sync_priv.h" diff --git a/drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c b/drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c index 786ab196a..087c93c2e 100644 --- a/drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c +++ b/drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include "channel_sync_priv.h" diff --git a/drivers/gpu/nvgpu/include/nvgpu/fence.h b/drivers/gpu/nvgpu/include/nvgpu/fence.h index 698c6dfc3..d85eb266f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/fence.h +++ b/drivers/gpu/nvgpu/include/nvgpu/fence.h @@ -34,6 +34,7 @@ struct nvgpu_semaphore; #endif struct nvgpu_os_fence; struct nvgpu_user_fence; +struct nvgpu_fence_ops; struct nvgpu_fence_type { /* Valid for all fence types: */ @@ -48,36 +49,13 @@ struct nvgpu_fence_type { struct nvgpu_cond *semaphore_wq; #endif +#ifdef CONFIG_TEGRA_GK20A_NVHOST /* Valid for fences created from syncpoints: */ struct nvgpu_nvhost_dev *nvhost_dev; u32 syncpt_id; u32 syncpt_value; -}; - -struct nvgpu_fence_ops { - int (*wait)(struct nvgpu_fence_type *f, u32 timeout); - bool (*is_expired)(struct nvgpu_fence_type *f); - void *(*free)(struct nvgpu_ref *ref); -}; - -#ifdef CONFIG_NVGPU_SW_SEMAPHORE -/* Fences can be created from semaphores or syncpoint (id, value) pairs */ -void nvgpu_fence_from_semaphore( - struct nvgpu_fence_type *f, - struct nvgpu_semaphore *semaphore, - struct nvgpu_cond *semaphore_wq, - struct nvgpu_os_fence os_fence); #endif - -void nvgpu_fence_from_syncpt( - struct nvgpu_fence_type *f, - struct nvgpu_nvhost_dev *nvhost_dev, - u32 id, u32 value, - struct nvgpu_os_fence os_fence); - -void nvgpu_fence_init(struct nvgpu_fence_type *f, - const struct nvgpu_fence_ops *ops, - struct nvgpu_os_fence os_fence); +}; /* Fence operations */ void nvgpu_fence_put(struct nvgpu_fence_type *f); diff --git a/drivers/gpu/nvgpu/include/nvgpu/fence_sema.h b/drivers/gpu/nvgpu/include/nvgpu/fence_sema.h new file mode 100644 index 000000000..e3fabbcc7 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/fence_sema.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_FENCE_SEMA_H +#define NVGPU_FENCE_SEMA_H + +#ifdef CONFIG_NVGPU_SW_SEMAPHORE + +void nvgpu_fence_from_semaphore( + struct nvgpu_fence_type *f, + struct nvgpu_semaphore *semaphore, + struct nvgpu_cond *semaphore_wq, + struct nvgpu_os_fence os_fence); + +#endif /* CONFIG_NVGPU_SW_SEMAPHORE */ + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/fence_syncpt.h b/drivers/gpu/nvgpu/include/nvgpu/fence_syncpt.h new file mode 100644 index 000000000..4c6001aaf --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/fence_syncpt.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_FENCE_SYNCPT_H +#define NVGPU_FENCE_SYNCPT_H + +#ifdef CONFIG_TEGRA_GK20A_NVHOST + +#include +#include + +struct nvgpu_fence_type; +struct nvgpu_nvhost_dev; + +void nvgpu_fence_from_syncpt( + struct nvgpu_fence_type *f, + struct nvgpu_nvhost_dev *nvhost_dev, + u32 id, u32 value, + struct nvgpu_os_fence os_fence); + +#endif /* CONFIG_TEGRA_GK20A_NVHOST */ + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/os_fence.h b/drivers/gpu/nvgpu/include/nvgpu/os_fence.h index 80a8b7c47..754db5075 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/os_fence.h +++ b/drivers/gpu/nvgpu/include/nvgpu/os_fence.h @@ -26,6 +26,7 @@ #define NVGPU_OS_FENCE_H #include +#include struct nvgpu_semaphore; struct nvgpu_channel;