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gpu: nvgpu: remove big page setting on pascal+

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We don't support big page size beginning Pascal, so set HAL
gops.fb.set_mmu_page_size() to NULL on all those platforms

Also remove these accessors from corresponding platforms
fb_mmu_ctrl_use_pdb_big_page_size_v()
fb_mmu_ctrl_use_pdb_big_page_size_true_f()
fb_mmu_ctrl_use_pdb_big_page_size_false_f()

Bug 2173122

Change-Id: I7353412860a7a6f8a993ca9184a0dc3ca9d749af
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1850946
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2018-09-28 14:54:45 +05:30
committed by Abdul Salam
parent ee6a5a32c9
commit 7ae214a5d1
9 changed files with 10 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/gk20a/mm_gk20a.c
View File

@@ -92,7 +92,10 @@ int gk20a_init_mm_setup_hw(struct gk20a *g)
nvgpu_log_fn(g, " ");
g->ops.fb.set_mmu_page_size(g);
if (g->ops.fb.set_mmu_page_size) {
g->ops.fb.set_mmu_page_size(g);
}
if (g->ops.fb.set_use_full_comp_tag_line) {
mm->use_full_comp_tag_line =
g->ops.fb.set_use_full_comp_tag_line(g);

2
drivers/gpu/nvgpu/gp106/hal_gp106.c
View File

@@ -408,7 +408,7 @@ static const struct gpu_ops gp106_ops = {
.fb = {
.init_hw = gm20b_fb_init_hw,
.init_fs_state = gp106_fb_init_fs_state,
.set_mmu_page_size = gm20b_fb_set_mmu_page_size,
.set_mmu_page_size = NULL,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
.mmu_ctrl = gm20b_fb_mmu_ctrl,

2
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -369,7 +369,7 @@ static const struct gpu_ops gp10b_ops = {
.fb = {
.init_hw = gm20b_fb_init_hw,
.init_fs_state = fb_gm20b_init_fs_state,
.set_mmu_page_size = gm20b_fb_set_mmu_page_size,
.set_mmu_page_size = NULL,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
.mmu_ctrl = gm20b_fb_mmu_ctrl,

2
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -470,7 +470,7 @@ static const struct gpu_ops gv100_ops = {
.fb = {
.init_hw = gv11b_fb_init_hw,
.init_fs_state = gp106_fb_init_fs_state,
.set_mmu_page_size = gm20b_fb_set_mmu_page_size,
.set_mmu_page_size = NULL,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
.mmu_ctrl = gm20b_fb_mmu_ctrl,

2
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -433,7 +433,7 @@ static const struct gpu_ops gv11b_ops = {
.init_hw = gv11b_fb_init_hw,
.init_fs_state = gv11b_fb_init_fs_state,
.init_cbc = gv11b_fb_init_cbc,
.set_mmu_page_size = gm20b_fb_set_mmu_page_size,
.set_mmu_page_size = NULL,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
.mmu_ctrl = gm20b_fb_mmu_ctrl,

14
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -76,18 +76,6 @@ static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
{
return (r >> 11U) & 0x1U;
}
static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
{
return 0x800U;
}
static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
{
return 0x0U;
}
static inline u32 fb_priv_mmu_phy_secure_r(void)
{
return 0x00100ce4U;

14
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -76,18 +76,6 @@ static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
{
return (r >> 11U) & 0x1U;
}
static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
{
return 0x800U;
}
static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
{
return 0x0U;
}
static inline u32 fb_priv_mmu_phy_secure_r(void)
{
return 0x00100ce4U;

12
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h
View File

@@ -152,18 +152,6 @@ static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
{
return (r >> 11U) & 0x1U;
}
static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
{
return 0x800U;
}
static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_ctrl_atomic_capability_mode_f(u32 v)
{
return (v & 0x3U) << 24U;

12
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
View File

@@ -76,18 +76,6 @@ static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
{
return (r >> 11U) & 0x1U;
}
static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
{
return 0x800U;
}
static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
{
return 0x0U;
}
static inline u32 fb_priv_mmu_phy_secure_r(void)
{
return 0x00100ce4U;