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gpu: nvgpu: remove unify_address_space enforcement

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Let nvrm_gpu decide if unified_address_space is required when requesting
new address space.

JIRA NVGPU_5302

Change-Id: Ib77be5e7c913802a01f7e7861e8bce3d47aed55f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2427724
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Sami Kiminki <skiminki@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Vedashree Vidwans
2020-10-13 23:42:07 -07:00
committed by Alex Waterman
parent a252cc244a
commit 7b4bff6ebf
5 changed files with 0 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/os/linux/pci.c
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@@ -107,7 +107,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
*/ */
.ch_wdt_init_limit_ms = 30000, .ch_wdt_init_limit_ms = 30000,
.unify_address_spaces = true,
.honors_aperture = true, .honors_aperture = true,
.dma_mask = DMA_BIT_MASK(40), .dma_mask = DMA_BIT_MASK(40),
.hardcode_sw_threshold = false, .hardcode_sw_threshold = false,
@@ -147,7 +146,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.ch_wdt_init_limit_ms = 7000, .ch_wdt_init_limit_ms = 7000,
.unify_address_spaces = true,
.honors_aperture = true, .honors_aperture = true,
.dma_mask = DMA_BIT_MASK(40), .dma_mask = DMA_BIT_MASK(40),
.hardcode_sw_threshold = false, .hardcode_sw_threshold = false,
@@ -187,7 +185,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.ch_wdt_init_limit_ms = 7000, .ch_wdt_init_limit_ms = 7000,
.unify_address_spaces = true,
.honors_aperture = true, .honors_aperture = true,
.dma_mask = DMA_BIT_MASK(40), .dma_mask = DMA_BIT_MASK(40),
.hardcode_sw_threshold = false, .hardcode_sw_threshold = false,
@@ -227,7 +224,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.ch_wdt_init_limit_ms = 7000, .ch_wdt_init_limit_ms = 7000,
.unify_address_spaces = true,
.honors_aperture = true, .honors_aperture = true,
.dma_mask = DMA_BIT_MASK(40), .dma_mask = DMA_BIT_MASK(40),
.hardcode_sw_threshold = false, .hardcode_sw_threshold = false,

1
drivers/gpu/nvgpu/os/linux/platform_gp10b_tegra.c
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@@ -588,7 +588,6 @@ struct gk20a_platform gp10b_tegra_platform = {
.soc_name = "tegra18x", .soc_name = "tegra18x",
.unified_memory = true, .unified_memory = true,
.unify_address_spaces = true,
.dma_mask = DMA_BIT_MASK(36), .dma_mask = DMA_BIT_MASK(36),
#ifdef CONFIG_NV_TEGRA_MC #ifdef CONFIG_NV_TEGRA_MC

1
drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
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@@ -335,7 +335,6 @@ struct gk20a_platform gv11b_tegra_platform = {
.honors_aperture = true, .honors_aperture = true,
.unified_memory = true, .unified_memory = true,
.unify_address_spaces = true,
.dma_mask = DMA_BIT_MASK(36), .dma_mask = DMA_BIT_MASK(36),
.reset_assert = gp10b_tegra_reset_assert, .reset_assert = gp10b_tegra_reset_assert,

1
drivers/gpu/nvgpu/os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c
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@@ -113,6 +113,5 @@ struct gk20a_platform gv11b_vgpu_tegra_platform = {
.resume = vgpu_tegra_resume, .resume = vgpu_tegra_resume,
.unified_memory = true, .unified_memory = true,
.unify_address_spaces = true,
.dma_mask = DMA_BIT_MASK(36), .dma_mask = DMA_BIT_MASK(36),
}; };

1
drivers/gpu/nvgpu/os/linux/vgpu/platform_vgpu_tegra.c
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@@ -98,5 +98,4 @@ struct gk20a_platform vgpu_tegra_platform = {
.resume = vgpu_tegra_resume, .resume = vgpu_tegra_resume,
.unified_memory = true, .unified_memory = true,
.unify_address_spaces = true,
}; };