gpu: nvgpu: volt: Remove unused code in volt_pmu.c

-Removed volt cmdhandler
-Removed volt set/get structures
-Removed volt set/get Macros

NVGPU-4372

Change-Id: I0de7698fd1d86e5ca6a8399481b790738b9cbf4c
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2243026
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
rmylavarapu
2019-11-20 11:45:27 +05:30
committed by Alex Waterman
parent 15c9355c69
commit 7b97d3f949
3 changed files with 0 additions and 85 deletions

View File

@@ -34,11 +34,6 @@
#include "volt_pmu.h"
struct volt_rpc_pmucmdhandler_params {
struct nv_pmu_volt_rpc *prpc_call;
u32 success;
};
int nvgpu_volt_send_load_cmd_to_pmu(struct gk20a *g)
{
struct nvgpu_pmu *pmu = g->pmu;
@@ -62,14 +57,6 @@ void nvgpu_pmu_volt_rpc_handler(struct gk20a *g, struct nv_pmu_rpc_header *rpc)
nvgpu_pmu_dbg(g,
"reply NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD");
break;
case NV_PMU_RPC_ID_VOLT_VOLT_SET_VOLTAGE:
nvgpu_pmu_dbg(g,
"reply NV_PMU_RPC_ID_VOLT_VOLT_SET_VOLTAGE");
break;
case NV_PMU_RPC_ID_VOLT_VOLT_RAIL_GET_VOLTAGE:
nvgpu_pmu_dbg(g,
"reply NV_PMU_RPC_ID_VOLT_VOLT_RAIL_GET_VOLTAGE");
break;
case NV_PMU_RPC_ID_VOLT_LOAD:
nvgpu_pmu_dbg(g,
"reply NV_PMU_RPC_ID_VOLT_LOAD");

View File

@@ -23,9 +23,6 @@
#ifndef NVGPU_VOLT_PMU_H
#define NVGPU_VOLT_PMU_H
#define RAIL_COUNT_GP 2
#define RAIL_COUNT_GV 1
u32 volt_pmu_send_load_cmd_to_pmu(struct gk20a *g);
#endif /* NVGPU_VOLT_PMU_H */

View File

@@ -227,34 +227,9 @@ union nv_pmu_volt_volt_policy_boardobj_get_status_union {
NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_policy);
struct nv_pmu_volt_policy_voltage_data {
u8 policy_idx;
struct ctrl_perf_volt_rail_list
rail_list;
};
struct nv_pmu_volt_rail_get_voltage {
u8 rail_idx;
u32 voltage_uv;
};
struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin {
u8 num_rails;
struct ctrl_volt_volt_rail_list
rail_list;
};
#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_SET (0x00000000U)
#define NV_PMU_VOLT_CMD_ID_RPC (0x00000001U)
#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002U)
#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN (0x00000004U)
/*
* PMU VOLT RPC calls.
*/
#define NV_PMU_VOLT_RPC_ID_LOAD (0x00000000U)
#define NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE (0x00000002U)
#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE (0x00000003U)
struct nv_pmu_volt_cmd_rpc {
u8 cmd_type;
@@ -274,19 +249,6 @@ struct nv_pmu_volt_cmd {
};
};
struct nv_pmu_volt_rpc {
u8 function;
bool b_supported;
bool b_success;
falcon_status flcn_status;
union {
struct nv_pmu_volt_policy_voltage_data volt_policy_voltage_data;
struct nv_pmu_volt_rail_get_voltage volt_rail_get_voltage;
struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin
volt_rail_set_noise_unaware_vmin;
} params;
};
/*
* VOLT MSG ID definitions
*/
@@ -348,35 +310,4 @@ struct nv_pmu_rpc_struct_volt_load {
u32 scratch[1];
};
/*
* Defines the structure that holds data
* used to execute VOLT_SET_VOLTAGE RPC.
*/
struct nv_pmu_rpc_struct_volt_volt_set_voltage {
/*[IN/OUT] Must be first field in RPC structure */
struct nv_pmu_rpc_header hdr;
/*[IN] ID of the client that wants to set the voltage */
u8 client_id;
/*
* [IN] The list containing target voltage and
* noise-unaware Vmin value for the VOLT_RAILs.
*/
struct ctrl_volt_volt_rail_list_v1 rail_list;
u32 scratch[1];
};
/*
* Defines the structure that holds data
* used to execute VOLT_RAIL_GET_VOLTAGE RPC.
*/
struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage {
/*[IN/OUT] Must be first field in RPC structure */
struct nv_pmu_rpc_header hdr;
/* [OUT] Current voltage in uv */
u32 voltage_uv;
/* [IN] Voltage Rail Table Index */
u8 rail_idx;
u32 scratch[1];
};
#endif /* NVGPU_PMUIF_VOLT_H */