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gpu: nvgpu: add support for pre-os FW
Pre-os firmware takes care, among others, of the control of FAN till the driver takes over its control. On some GPUs not enabling this FW can lead tp physical board damage, hence it is needed to run this firmware. JIRA: NVGPUGV100-9 Change-Id: I18d54cfd5eb64ecec79c5dae67ac8d5bb1facf36 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1549035 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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@@ -239,6 +239,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
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.honors_aperture = true,
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.honors_aperture = true,
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.vbios_min_version = 0x88001e00,
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.vbios_min_version = 0x88001e00,
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.hardcode_sw_threshold = false,
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.hardcode_sw_threshold = false,
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.run_preos = true,
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},
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},
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{ /* DEVICE=PG503 SKU 200 ES */
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{ /* DEVICE=PG503 SKU 200 ES */
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/* ptimer src frequency in hz */
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/* ptimer src frequency in hz */
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@@ -272,6 +273,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
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.honors_aperture = true,
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.honors_aperture = true,
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.vbios_min_version = 0x88001e00,
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.vbios_min_version = 0x88001e00,
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.hardcode_sw_threshold = false,
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.hardcode_sw_threshold = false,
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.run_preos = true,
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}
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}
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};
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};
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@@ -187,8 +187,8 @@ int gk20a_finalize_poweron(struct gk20a *g)
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nvgpu_flcn_sw_init(g, FALCON_ID_PMU);
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nvgpu_flcn_sw_init(g, FALCON_ID_PMU);
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nvgpu_flcn_sw_init(g, FALCON_ID_SEC2);
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nvgpu_flcn_sw_init(g, FALCON_ID_SEC2);
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if (g->ops.bios_init)
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if (g->ops.bios.init)
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err = g->ops.bios_init(g);
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err = g->ops.bios.init(g);
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if (err)
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if (err)
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goto done;
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goto done;
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@@ -969,7 +969,11 @@ struct gpu_ops {
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int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst);
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int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst);
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} bus;
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} bus;
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int (*bios_init)(struct gk20a *g);
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struct {
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int (*init)(struct gk20a *g);
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int (*preos_wait_for_halt)(struct gk20a *g);
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void (*preos_reload_check)(struct gk20a *g);
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} bios;
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#if defined(CONFIG_GK20A_CYCLE_STATS)
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#if defined(CONFIG_GK20A_CYCLE_STATS)
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struct {
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struct {
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@@ -135,6 +135,16 @@ out:
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return err;
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return err;
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}
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}
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int gp106_bios_preos_wait_for_halt(struct gk20a *g)
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{
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int err = 0;
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if (nvgpu_flcn_wait_for_halt(g->pmu.flcn, PMU_BOOT_TIMEOUT_MAX / 1000))
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err = -ETIMEDOUT;
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return err;
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}
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static int gp106_bios_preos(struct gk20a *g)
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static int gp106_bios_preos(struct gk20a *g)
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{
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{
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int err = 0;
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int err = 0;
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@@ -146,6 +156,9 @@ static int gp106_bios_preos(struct gk20a *g)
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goto out;
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goto out;
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}
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}
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if (g->ops.bios.preos_reload_check)
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g->ops.bios.preos_reload_check(g);
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upload_code(g, g->bios.preos.bootloader_phys_base,
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upload_code(g, g->bios.preos.bootloader_phys_base,
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g->bios.preos.bootloader,
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g->bios.preos.bootloader,
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g->bios.preos.bootloader_size,
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g->bios.preos.bootloader_size,
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@@ -161,11 +174,7 @@ static int gp106_bios_preos(struct gk20a *g)
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nvgpu_flcn_bootstrap(g->pmu.flcn, g->bios.preos.code_entry_point);
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nvgpu_flcn_bootstrap(g->pmu.flcn, g->bios.preos.code_entry_point);
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if (nvgpu_flcn_wait_for_halt(g->pmu.flcn,
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err = g->ops.bios.preos_wait_for_halt(g);
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PMU_BOOT_TIMEOUT_MAX / 1000)) {
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err = -ETIMEDOUT;
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goto out;
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}
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nvgpu_flcn_clear_halt_intr_status(g->pmu.flcn,
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nvgpu_flcn_clear_halt_intr_status(g->pmu.flcn,
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gk20a_get_gr_idle_timeout(g));
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gk20a_get_gr_idle_timeout(g));
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@@ -27,6 +27,5 @@ struct gk20a;
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struct gpu_ops;
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struct gpu_ops;
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int gp106_bios_init(struct gk20a *g);
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int gp106_bios_init(struct gk20a *g);
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void gp106_init_bios_ops(struct gpu_ops *gops);
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int gp106_bios_preos_wait_for_halt(struct gk20a *g);
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#endif
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#endif
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@@ -216,6 +216,10 @@ static int gp106_init_gpu_characteristics(struct gk20a *g)
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}
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}
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static const struct gpu_ops gp106_ops = {
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static const struct gpu_ops gp106_ops = {
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.bios = {
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.init = gp106_bios_init,
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.preos_wait_for_halt = gp106_bios_preos_wait_for_halt,
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},
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.ltc = {
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.ltc = {
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.determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
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.determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
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.set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
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.set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
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@@ -695,7 +699,6 @@ static const struct gpu_ops gp106_ops = {
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},
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},
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.get_litter_value = gp106_get_litter_value,
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.get_litter_value = gp106_get_litter_value,
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.chip_init_gpu_characteristics = gp106_init_gpu_characteristics,
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.chip_init_gpu_characteristics = gp106_init_gpu_characteristics,
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.bios_init = gp106_bios_init,
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};
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};
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int gp106_init_hal(struct gk20a *g)
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int gp106_init_hal(struct gk20a *g)
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@@ -705,6 +708,7 @@ int gp106_init_hal(struct gk20a *g)
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gk20a_dbg_fn("");
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gk20a_dbg_fn("");
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gops->bios = gp106_ops.bios;
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gops->ltc = gp106_ops.ltc;
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gops->ltc = gp106_ops.ltc;
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gops->ce2 = gp106_ops.ce2;
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gops->ce2 = gp106_ops.ce2;
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gops->gr = gp106_ops.gr;
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gops->gr = gp106_ops.gr;
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@@ -747,7 +751,6 @@ int gp106_init_hal(struct gk20a *g)
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gops->get_litter_value = gp106_ops.get_litter_value;
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gops->get_litter_value = gp106_ops.get_litter_value;
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gops->chip_init_gpu_characteristics =
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gops->chip_init_gpu_characteristics =
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gp106_ops.chip_init_gpu_characteristics;
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gp106_ops.chip_init_gpu_characteristics;
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gops->bios_init = gp106_ops.bios_init;
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__nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
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__nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
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__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
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__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
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