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gpu: nvgpu: fix MISRA 17.1 in logging functions

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MISRA Rule 17.1 forbids use of stdarg.h features which are defined for
variable arguments.
This patch modifies logging macros to use slogf function for QNX builds.
This avoids use of variable argument functions used for formatting log
message.

Jira NVGPU-4075

Change-Id: I5b6bb1107a7e431afaa960003858193a477b2ee6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2192016
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2019-10-03 16:37:57 -07:00
committed by Alex Waterman
parent 7a62265dde
commit 7c98fbba42
16 changed files with 282 additions and 139 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
arch/nvgpu-common.yaml
View File

@@ -68,6 +68,12 @@ ecc:
include/nvgpu/ecc.h ]
deps:
log:
safe: yes
owner: Vedashree V
sources: [ common/log_common.c ]
deps:
# Pretty sure this can be marked as not-safe since we plan to use
# usermode submits in the safety build.
fence:
@@ -203,8 +209,7 @@ utils:
common/utils/string.c,
common/utils/worker.c,
common/utils/rbtree.c,
common/utils/enabled.c,
common/utils/assert.c ]
common/utils/enabled.c ]
##
## Common elements.

2
arch/nvgpu-interface.yaml
View File

@@ -76,7 +76,7 @@ lock:
log:
safe: yes
sources: [ include/nvgpu/log.h ]
sources: [ include/nvgpu/log.h, include/nvgpu/log_common.h ]
log2:
safe: yes

1
arch/nvgpu-linux.yaml
View File

@@ -234,6 +234,7 @@ headers:
include/nvgpu/linux/sim.h,
include/nvgpu/linux/sim_pci.h,
include/nvgpu/linux/thread.h,
include/nvgpu/linux/log.h,
include/nvgpu/linux/vm.h ]
# An extra unit to lump all the unclassified Linux files.

1
arch/nvgpu-posix.yaml
View File

@@ -43,6 +43,7 @@ headers:
include/nvgpu/posix/circ_buf.h,
include/nvgpu/posix/dma.h,
include/nvgpu/posix/io.h,
include/nvgpu/posix/log.h,
include/nvgpu/posix/log2.h,
include/nvgpu/posix/nvgpu_mem.h,
include/nvgpu/posix/pci.h,

4
drivers/gpu/nvgpu/Kconfig
View File

@@ -174,11 +174,11 @@ config NVGPU_COMPRESSION
Support for compression
config NVGPU_LOGGING
bool "Logging for non-safety build"
bool "NVGPU logging"
depends on GK20A
default y
help
Enable/Disable logging for non-safety builds
Enable/Disable NVGPU logging
config NVGPU_HAL_NON_FUSA
bool "Support non-functionally safe HALs"

2
drivers/gpu/nvgpu/Makefile
View File

@@ -78,7 +78,6 @@ obj-$(CONFIG_GK20A) := nvgpu.o
# is in progress.
nvgpu-y += \
common/utils/assert.o \
common/utils/enabled.o \
common/utils/rbtree.o \
common/utils/string.o \
@@ -514,6 +513,7 @@ nvgpu-y += \
common/fifo/userd.o \
common/fence/fence.o \
common/ecc.o \
common/log_common.o \
common/ce/ce.o \
common/ce/ce_app.o \
common/debugger.o

4
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -82,8 +82,7 @@ srcs += os/posix/bug.c \
os/posix/kmem.c \
os/posix/file_ops.c
srcs += common/utils/assert.c \
common/utils/enabled.c \
srcs += common/utils/enabled.c \
common/utils/rbtree.c \
common/utils/string.c \
common/utils/worker.c \
@@ -105,6 +104,7 @@ srcs += common/utils/assert.c \
common/fbp/fbp.c \
common/io/io.c \
common/ecc.c \
common/log_common.c \
common/falcon/falcon.c \
common/falcon/falcon_sw_gk20a.c \
common/gr/gr.c \

16
drivers/gpu/nvgpu/common/utils/assert.c → drivers/gpu/nvgpu/common/log_common.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,18 +20,10 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>
#include <nvgpu/log.h>
#include <nvgpu/gk20a.h>
void nvgpu_do_assert_print(struct gk20a *g, const char *fmt, ...)
bool nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask)
{
#ifdef CONFIG_NVGPU_LOGGING
va_list args;
va_start(args, fmt);
nvgpu_err(g, fmt, args);
va_end(args);
#endif
nvgpu_do_assert();
return (g->log_mask & log_mask) != 0ULL;
}

7
drivers/gpu/nvgpu/include/nvgpu/bug.h
View File

@@ -83,6 +83,11 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
}
struct gk20a;
void nvgpu_do_assert_print(struct gk20a *g, const char *fmt, ...);
#define nvgpu_do_assert_print(g, fmt, arg...) \
do { \
nvgpu_err(g, fmt, ##arg); \
nvgpu_do_assert(); \
} while (false)
#endif /* NVGPU_BUG_H */

71
drivers/gpu/nvgpu/include/nvgpu/linux/log.h Normal file
View File

@@ -0,0 +1,71 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef NVGPU_LINUX_LOG_H
#define NVGPU_LINUX_LOG_H
#include <nvgpu/types.h>
#include <nvgpu/bitops.h>
#include <nvgpu/log_common.h>
struct gk20a;
__attribute__((format (printf, 5, 6)))
void nvgpu_log_msg_impl(struct gk20a *g, const char *func_name, int line,
enum nvgpu_log_type type, const char *fmt, ...);
__attribute__((format (printf, 5, 6)))
void nvgpu_log_dbg_impl(struct gk20a *g, u64 log_mask,
const char *func_name, int line,
const char *fmt, ...);
/**
* nvgpu_log_impl - Print a debug message
*/
#define nvgpu_log_impl(g, log_mask, fmt, arg...) \
nvgpu_log_dbg_impl(g, log_mask, __func__, __LINE__, fmt, ##arg)
/**
* nvgpu_err_impl - Print an error
*/
#define nvgpu_err_impl(g, fmt, arg...) \
nvgpu_log_msg_impl(g, __func__, __LINE__, NVGPU_ERROR, fmt, ##arg)
/**
* nvgpu_warn_impl - Print a warning
*/
#define nvgpu_warn_impl(g, fmt, arg...) \
nvgpu_log_msg_impl(g, __func__, __LINE__, NVGPU_WARNING, fmt, ##arg)
/**
* nvgpu_info_impl - Print an info message
*/
#define nvgpu_info_impl(g, fmt, arg...) \
nvgpu_log_msg_impl(g, __func__, __LINE__, NVGPU_INFO, fmt, ##arg)
/*
* Deprecated API. Do not use!!
*/
#define gk20a_dbg_impl(log_mask, fmt, arg...) \
do { \
if (((log_mask) & NVGPU_DEFAULT_DBG_MASK) != 0) { \
nvgpu_log_msg_impl(NULL, __func__, __LINE__, \
NVGPU_DEBUG, fmt "\n", ##arg); \
} \
} while (false)
#endif

103
drivers/gpu/nvgpu/include/nvgpu/log.h
View File

@@ -23,101 +23,26 @@
#ifndef NVGPU_LOG_H
#define NVGPU_LOG_H
#include <nvgpu/types.h>
#include <nvgpu/bitops.h>
struct gk20a;
enum nvgpu_log_type {
NVGPU_ERROR = 0,
NVGPU_WARNING,
NVGPU_DEBUG,
NVGPU_INFO,
};
/*
* Each OS must implement these functions. They handle the OS specific nuances
* of printing data to a UART, log, whatever.
*/
#ifdef CONFIG_NVGPU_LOGGING
__attribute__((format (printf, 5, 6)))
void nvgpu_log_msg_impl(struct gk20a *g, const char *func_name, int line,
enum nvgpu_log_type type, const char *fmt, ...);
__attribute__((format (printf, 5, 6)))
void nvgpu_log_dbg_impl(struct gk20a *g, u64 log_mask,
const char *func_name, int line,
const char *fmt, ...);
#ifdef __KERNEL__
#include <nvgpu/linux/log.h>
#elif defined(__NVGPU_POSIX__)
#include <nvgpu/posix/log.h>
#else
static inline void nvgpu_log_msg_impl(struct gk20a *g, const char *func_name,
int line, enum nvgpu_log_type type, const char *fmt, ...)
{
}
static inline void nvgpu_log_dbg_impl(struct gk20a *g, u64 log_mask,
const char *func_name, int line,
const char *fmt, ...)
{
}
#include <nvgpu_rmos/include/log.h>
#endif
/*
* Use this define to set a default mask.
*/
#define NVGPU_DEFAULT_DBG_MASK (0)
#define gpu_dbg_info BIT(0) /* Lightly verbose info. */
#define gpu_dbg_fn BIT(1) /* Function name tracing. */
#define gpu_dbg_reg BIT(2) /* Register accesses; very verbose. */
#define gpu_dbg_pte BIT(3) /* GMMU PTEs. */
#define gpu_dbg_intr BIT(4) /* Interrupts. */
#define gpu_dbg_pmu BIT(5) /* gk20a pmu. */
#define gpu_dbg_clk BIT(6) /* gk20a clk. */
#define gpu_dbg_map BIT(7) /* Memory mappings. */
#define gpu_dbg_map_v BIT(8) /* Verbose mem mappings. */
#define gpu_dbg_gpu_dbg BIT(9) /* GPU debugger/profiler. */
#define gpu_dbg_cde BIT(10) /* cde info messages. */
#define gpu_dbg_cde_ctx BIT(11) /* cde context usage messages. */
#define gpu_dbg_ctxsw BIT(12) /* ctxsw tracing. */
#define gpu_dbg_sched BIT(13) /* Sched control tracing. */
#define gpu_dbg_sema BIT(14) /* Semaphore debugging. */
#define gpu_dbg_sema_v BIT(15) /* Verbose semaphore debugging. */
#define gpu_dbg_pmu_pstate BIT(16) /* p state controlled by pmu. */
#define gpu_dbg_xv BIT(17) /* XVE debugging. */
#define gpu_dbg_shutdown BIT(18) /* GPU shutdown tracing. */
#define gpu_dbg_kmem BIT(19) /* Kmem tracking debugging. */
#define gpu_dbg_pd_cache BIT(20) /* PD cache traces. */
#define gpu_dbg_alloc BIT(21) /* Allocator debugging. */
#define gpu_dbg_dma BIT(22) /* DMA allocation prints. */
#define gpu_dbg_sgl BIT(23) /* SGL related traces. */
#ifdef CONFIG_NVGPU_DGPU
#define gpu_dbg_vidmem BIT(24) /* VIDMEM tracing. */
#endif
#define gpu_dbg_nvlink BIT(25) /* nvlink Operation tracing. */
#define gpu_dbg_clk_arb BIT(26) /* Clk arbiter debugging. */
#define gpu_dbg_event BIT(27) /* Events to User debugging. */
#define gpu_dbg_vsrv BIT(28) /* server debugging. */
#define gpu_dbg_mem BIT(31) /* memory accesses; very verbose. */
/**
* nvgpu_log_mask_enabled - Check if logging is enabled
*
* @g - The GPU.
* @log_mask - The mask the check against.
* @log_mask - The mask to check against.
*
* Check if, given the passed mask, logging would actually happen. This is
* useful for avoiding calling the logging function many times when we know that
* said prints would not happen. For example for-loops of log statements in
* critical paths.
*/
#ifdef CONFIG_NVGPU_LOGGING
bool nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask);
#else
static inline bool nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask)
{
return false;
}
#endif
/**
* nvgpu_log - Print a debug message
@@ -131,7 +56,7 @@ static inline bool nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask)
* Print a message if the log_mask matches the enabled debugging.
*/
#define nvgpu_log(g, log_mask, fmt, arg...) \
nvgpu_log_dbg_impl(g, log_mask, __func__, __LINE__, fmt, ##arg)
nvgpu_log_impl(g, log_mask, fmt, ##arg)
/**
* nvgpu_err - Print an error
@@ -143,7 +68,7 @@ static inline bool nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask)
* Uncondtionally print an error message.
*/
#define nvgpu_err(g, fmt, arg...) \
nvgpu_log_msg_impl(g, __func__, __LINE__, NVGPU_ERROR, fmt, ##arg)
nvgpu_err_impl(g, fmt, ##arg)
/**
* nvgpu_err - Print a warning
@@ -155,7 +80,7 @@ static inline bool nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask)
* Uncondtionally print a warming message.
*/
#define nvgpu_warn(g, fmt, arg...) \
nvgpu_log_msg_impl(g, __func__, __LINE__, NVGPU_WARNING, fmt, ##arg)
nvgpu_warn_impl(g, fmt, ##arg)
/**
* nvgpu_info - Print an info message
@@ -167,7 +92,7 @@ static inline bool nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask)
* Unconditionally print an information message.
*/
#define nvgpu_info(g, fmt, arg...) \
nvgpu_log_msg_impl(g, __func__, __LINE__, NVGPU_INFO, fmt, ##arg)
nvgpu_info_impl(g, fmt, ##arg)
/*
* Some convenience macros.
@@ -189,15 +114,9 @@ static inline bool nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask)
* This exist for backwards compatibility with the old debug/logging API. If you
* want ftrace support use the new API!
*/
extern u64 nvgpu_dbg_mask;
#define gk20a_dbg(log_mask, fmt, arg...) \
do { \
if (((log_mask) & nvgpu_dbg_mask) != 0) { \
nvgpu_log_msg_impl(NULL, __func__, __LINE__, \
NVGPU_DEBUG, fmt "\n", ##arg); \
} \
} while (false)
gk20a_dbg_impl(log_mask, fmt, ##arg)
/*
* Some convenience macros.

71
drivers/gpu/nvgpu/include/nvgpu/log_common.h Normal file
View File

@@ -0,0 +1,71 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_LOG_COMMON_H
#define NVGPU_LOG_COMMON_H
enum nvgpu_log_type {
NVGPU_ERROR = 0,
NVGPU_WARNING,
NVGPU_DEBUG,
NVGPU_INFO,
};
/*
* Use this define to set a default mask.
*/
#define NVGPU_DEFAULT_DBG_MASK (0)
#define gpu_dbg_info BIT(0) /* Lightly verbose info. */
#define gpu_dbg_fn BIT(1) /* Function name tracing. */
#define gpu_dbg_reg BIT(2) /* Register accesses; very verbose. */
#define gpu_dbg_pte BIT(3) /* GMMU PTEs. */
#define gpu_dbg_intr BIT(4) /* Interrupts. */
#define gpu_dbg_pmu BIT(5) /* gk20a pmu. */
#define gpu_dbg_clk BIT(6) /* gk20a clk. */
#define gpu_dbg_map BIT(7) /* Memory mappings. */
#define gpu_dbg_map_v BIT(8) /* Verbose mem mappings. */
#define gpu_dbg_gpu_dbg BIT(9) /* GPU debugger/profiler. */
#define gpu_dbg_cde BIT(10) /* cde info messages. */
#define gpu_dbg_cde_ctx BIT(11) /* cde context usage messages. */
#define gpu_dbg_ctxsw BIT(12) /* ctxsw tracing. */
#define gpu_dbg_sched BIT(13) /* Sched control tracing. */
#define gpu_dbg_sema BIT(14) /* Semaphore debugging. */
#define gpu_dbg_sema_v BIT(15) /* Verbose semaphore debugging. */
#define gpu_dbg_pmu_pstate BIT(16) /* p state controlled by pmu. */
#define gpu_dbg_xv BIT(17) /* XVE debugging. */
#define gpu_dbg_shutdown BIT(18) /* GPU shutdown tracing. */
#define gpu_dbg_kmem BIT(19) /* Kmem tracking debugging. */
#define gpu_dbg_pd_cache BIT(20) /* PD cache traces. */
#define gpu_dbg_alloc BIT(21) /* Allocator debugging. */
#define gpu_dbg_dma BIT(22) /* DMA allocation prints. */
#define gpu_dbg_sgl BIT(23) /* SGL related traces. */
#ifdef CONFIG_NVGPU_DGPU
#define gpu_dbg_vidmem BIT(24) /* VIDMEM tracing. */
#endif
#define gpu_dbg_nvlink BIT(25) /* nvlink Operation tracing. */
#define gpu_dbg_clk_arb BIT(26) /* Clk arbiter debugging. */
#define gpu_dbg_event BIT(27) /* Events to User debugging. */
#define gpu_dbg_vsrv BIT(28) /* server debugging. */
#define gpu_dbg_mem BIT(31) /* memory accesses; very verbose. */
#endif

77
drivers/gpu/nvgpu/include/nvgpu/posix/log.h Normal file
View File

@@ -0,0 +1,77 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_POSIX_LOG_H
#define NVGPU_POSIX_LOG_H
#include <nvgpu/types.h>
#include <nvgpu/bitops.h>
#include <nvgpu/log_common.h>
struct gk20a;
__attribute__((format (printf, 5, 6)))
void nvgpu_log_msg_impl(struct gk20a *g, const char *func_name, int line,
enum nvgpu_log_type type, const char *fmt, ...);
__attribute__((format (printf, 5, 6)))
void nvgpu_log_dbg_impl(struct gk20a *g, u64 log_mask,
const char *func_name, int line,
const char *fmt, ...);
/**
* nvgpu_log_impl - Print a debug message
*/
#define nvgpu_log_impl(g, log_mask, fmt, arg...) \
nvgpu_log_dbg_impl(g, log_mask, __func__, __LINE__, fmt, ##arg)
/**
* nvgpu_err_impl - Print an error
*/
#define nvgpu_err_impl(g, fmt, arg...) \
nvgpu_log_msg_impl(g, __func__, __LINE__, NVGPU_ERROR, fmt, ##arg)
/**
* nvgpu_warn_impl - Print a warning
*/
#define nvgpu_warn_impl(g, fmt, arg...) \
nvgpu_log_msg_impl(g, __func__, __LINE__, NVGPU_WARNING, fmt, ##arg)
/**
* nvgpu_info_impl - Print an info message
*/
#define nvgpu_info_impl(g, fmt, arg...) \
nvgpu_log_msg_impl(g, __func__, __LINE__, NVGPU_INFO, fmt, ##arg)
/*
* Deprecated API. Do not use!!
*/
#define gk20a_dbg_impl(log_mask, fmt, arg...) \
do { \
if (((log_mask) & NVGPU_DEFAULT_DBG_MASK) != 0) { \
nvgpu_log_msg_impl(NULL, __func__, __LINE__, \
NVGPU_DEBUG, fmt "\n", ##arg); \
} \
} while (false)
#endif

7
drivers/gpu/nvgpu/os/linux/log.c
View File

@@ -17,7 +17,7 @@
#include <linux/kernel.h>
#include <linux/device.h>
#include <nvgpu/log.h>
#include <nvgpu/linux/log.h>
#include <nvgpu/gk20a.h>
#include "platform_gk20a.h"
@@ -45,11 +45,6 @@ static const char *log_types[] = {
"INFO",
};
bool nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask)
{
return (g->log_mask & log_mask) != 0ULL;
}
static inline const char *nvgpu_log_name(struct gk20a *g)
{
return dev_name(dev_from_gk20a(g));

9
drivers/gpu/nvgpu/os/posix/log.c
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/log.h>
#include <nvgpu/posix/log.h>
#include <nvgpu/types.h>
#include <nvgpu/gk20a.h>
@@ -36,8 +36,6 @@
*/
#define LOG_FMT "nvgpu: %s %33s:%-4d [%-4s] %s\n"
u64 nvgpu_dbg_mask = NVGPU_DEFAULT_DBG_MASK;
static const char *log_types[] = {
"ERR",
"WRN",
@@ -50,11 +48,6 @@ static inline const char *nvgpu_log_name(struct gk20a *g)
return "gpu.USS";
}
bool nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask)
{
return (g->log_mask & log_mask) != 0ULL;
}
static void __nvgpu_really_print_log(const char *gpu_name,
const char *func_name, int line,
enum nvgpu_log_type type, const char *log)

35
drivers/gpu/nvgpu/os/posix/os_sched.c
View File

@@ -42,31 +42,44 @@ int nvgpu_current_tid(struct gk20a *g)
void nvgpu_print_current_impl(struct gk20a *g, const char *func_name, int line,
void *ctx, enum nvgpu_log_type type)
{
char *log_message = "(unknown process)";
#if defined(__NVGPU_POSIX__)
#ifdef _GNU_SOURCE
char current_tname[CURRENT_NAME_LEN];
/* pthread_getname_np() will return null terminated string on success */
if (pthread_getname_np(0, current_tname, CURRENT_NAME_LEN) == 0) {
nvgpu_log_msg_impl(g, func_name, line, type, "%s",
current_tname);
} else {
nvgpu_log_msg_impl(g, func_name, line, type,
"(unknown process)");
log_message = current_tname;
}
#else
nvgpu_log_msg_impl(g, func_name, line, type, "(unknown process)");
nvgpu_err(g, "(unknown process)");
return;
#endif
#else
char current_tname[CURRENT_NAME_LEN];
/* pthread_getname_np() will return null terminated string on success */
if (pthread_getname_np(0, current_tname, CURRENT_NAME_LEN) == 0) {
nvgpu_log_msg_impl(g, func_name, line, type, "%s",
current_tname);
} else {
nvgpu_log_msg_impl(g, func_name, line, type,
"(unknown process)");
log_message = current_tname;
}
#endif
switch (type) {
case NVGPU_ERROR:
nvgpu_err(g, "%s", log_message);
break;
case NVGPU_WARNING:
nvgpu_warn(g, "%s", log_message);
break;
case NVGPU_DEBUG:
nvgpu_log(g, 0U, "%s", log_message);
break;
case NVGPU_INFO:
nvgpu_info(g, "%s", log_message);
break;
default:
nvgpu_err(g, "%s", log_message);
break;
}
}