From 7cae3709e003943df1770d35a6737c46b081e5ee Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Fri, 19 Jul 2019 11:49:31 +0530 Subject: [PATCH] gpu: nvgpu: split fb fusa/non-fusa hal Moved gv11b_fb_intr_inject_hubmmu_ecc_error from fb_intr_ecc_gv11b.c to fusa version and deleted that file. Moved debugger related functions from fb_gm20b.c to fusa version. Updated arch yaml to reflect the fusa and non-fusa fb units. JIRA NVGPU-3690 Change-Id: I929169e9aac62e8377e4ea7e8353caa970999299 Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/2156879 Reviewed-by: Deepak Nibade GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- arch/nvgpu-hal-new.yaml | 21 +++++---- drivers/gpu/nvgpu/Makefile | 1 - drivers/gpu/nvgpu/Makefile.sources | 5 +-- drivers/gpu/nvgpu/hal/fb/fb_gm20b.c | 29 ------------ drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c | 29 ++++++++++++ .../gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b.c | 44 ------------------- .../hal/fb/intr/fb_intr_ecc_gv11b_fusa.c | 12 +++++ 7 files changed, 55 insertions(+), 86 deletions(-) delete mode 100644 drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b.c diff --git a/arch/nvgpu-hal-new.yaml b/arch/nvgpu-hal-new.yaml index a8b37d28c..eeb732fae 100644 --- a/arch/nvgpu-hal-new.yaml +++ b/arch/nvgpu-hal-new.yaml @@ -523,25 +523,28 @@ mc: hal/mc/mc_tu104.c, hal/mc/mc_tu104.h ] -fb: +fb_fusa: safe: yes owner: Seshendra G - sources: [ hal/fb/fb_gm20b.c, - hal/fb/fb_gm20b_fusa.c, + sources: [ hal/fb/fb_gm20b_fusa.c, hal/fb/fb_gm20b.h, + hal/fb/fb_gv11b_fusa.c, + hal/fb/fb_gv11b.h, + hal/fb/intr/fb_intr_gv11b.h, hal/fb/intr/fb_intr_gv11b_fusa.c, + hal/fb/fb_mmu_fault_gv11b.h, hal/fb/fb_mmu_fault_gv11b_fusa.c, + hal/fb/intr/fb_intr_ecc_gv11b.h, hal/fb/intr/fb_intr_ecc_gv11b_fusa.c ] + +fb: + safe: no + owner: Seshendra G + sources: [ hal/fb/fb_gm20b.c, hal/fb/fb_gp106.c, hal/fb/fb_gp106.h, hal/fb/fb_gp10b.c, hal/fb/fb_gp10b.h, hal/fb/fb_gv100.c, hal/fb/fb_gv100.h, hal/fb/fb_gv11b.c, - hal/fb/fb_gv11b_fusa.c, - hal/fb/fb_gv11b.h, hal/fb/fb_tu104.c, hal/fb/fb_tu104.h, hal/fb/intr/fb_intr_gv100.h, hal/fb/intr/fb_intr_gv100.c, - hal/fb/intr/fb_intr_gv11b.h, hal/fb/intr/fb_intr_gv11b_fusa.c, - hal/fb/fb_mmu_fault_gv11b.h, hal/fb/fb_mmu_fault_gv11b_fusa.c, hal/fb/fb_mmu_fault_tu104.h, hal/fb/fb_mmu_fault_tu104.c, - hal/fb/intr/fb_intr_ecc_gv11b.h, hal/fb/intr/fb_intr_ecc_gv11b.c, - hal/fb/intr/fb_intr_ecc_gv11b_fusa.c, hal/fb/intr/fb_intr_tu104.c, hal/fb/intr/fb_intr_tu104.h ] pmu_fusa: diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 67a3c8705..ad7592f8a 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -253,7 +253,6 @@ nvgpu-y += \ hal/fb/fb_mmu_fault_tu104.o \ hal/fb/intr/fb_intr_gv100.o \ hal/fb/intr/fb_intr_tu104.o \ - hal/fb/intr/fb_intr_ecc_gv11b.o \ hal/fuse/fuse_gm20b.o \ hal/fuse/fuse_gp106.o \ hal/func/func_tu104.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 1da10d140..5bf5a1a5a 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -149,9 +149,6 @@ srcs += common/utils/enabled.c \ hal/init/hal_gv11b_litter.c \ hal/init/hal_init.c \ hal/power_features/cg/gv11b_gating_reglist.c \ - hal/fb/fb_gm20b.c \ - hal/fb/fb_gv11b.c \ - hal/fb/intr/fb_intr_ecc_gv11b.c \ hal/fifo/runlist_fifo_gk20a.c \ hal/fifo/runlist_fifo_gv11b.c \ hal/fifo/runlist_ram_gk20a.c \ @@ -288,6 +285,8 @@ srcs += hal/init/hal_gp10b.c \ hal/ltc/intr/ltc_intr_gp10b.c \ hal/fb/fb_gp10b.c \ hal/fb/fb_gp106.c \ + hal/fb/fb_gm20b.c \ + hal/fb/fb_gv11b.c \ hal/fuse/fuse_gm20b.c \ hal/rc/rc_gk20a.c \ hal/fifo/fifo_gk20a.c \ diff --git a/drivers/gpu/nvgpu/hal/fb/fb_gm20b.c b/drivers/gpu/nvgpu/hal/fb/fb_gm20b.c index 5a969f8be..ed2dbb50e 100644 --- a/drivers/gpu/nvgpu/hal/fb/fb_gm20b.c +++ b/drivers/gpu/nvgpu/hal/fb/fb_gm20b.c @@ -91,32 +91,3 @@ u64 gm20b_fb_compression_align_mask(struct gk20a *g) return SZ_64K - 1UL; } #endif - -#ifdef CONFIG_NVGPU_DEBUGGER -bool gm20b_fb_debug_mode_enabled(struct gk20a *g) -{ - u32 debug_ctrl = gk20a_readl(g, fb_mmu_debug_ctrl_r()); - return fb_mmu_debug_ctrl_debug_v(debug_ctrl) == - fb_mmu_debug_ctrl_debug_enabled_v(); -} - -void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) -{ - u32 reg_val, fb_debug_ctrl; - - if (enable) { - fb_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f(); - g->mmu_debug_ctrl = true; - } else { - fb_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f(); - g->mmu_debug_ctrl = false; - } - - reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r()); - reg_val = set_field(reg_val, - fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl); - gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); - - g->ops.gr.set_debug_mode(g, enable); -} -#endif diff --git a/drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c index a97eaf90d..9ef81b2a1 100644 --- a/drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c @@ -42,6 +42,35 @@ #define VPR_INFO_FETCH_WAIT (5) #define WPR_INFO_ADDR_ALIGNMENT 0x0000000c +#ifdef CONFIG_NVGPU_DEBUGGER +bool gm20b_fb_debug_mode_enabled(struct gk20a *g) +{ + u32 debug_ctrl = gk20a_readl(g, fb_mmu_debug_ctrl_r()); + return fb_mmu_debug_ctrl_debug_v(debug_ctrl) == + fb_mmu_debug_ctrl_debug_enabled_v(); +} + +void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) +{ + u32 reg_val, fb_debug_ctrl; + + if (enable) { + fb_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f(); + g->mmu_debug_ctrl = true; + } else { + fb_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f(); + g->mmu_debug_ctrl = false; + } + + reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r()); + reg_val = set_field(reg_val, + fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl); + gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); + + g->ops.gr.set_debug_mode(g, enable); +} +#endif + void gm20b_fb_init_hw(struct gk20a *g) { u64 addr = nvgpu_mem_get_addr(g, &g->mm.sysmem_flush) >> 8; diff --git a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b.c b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b.c deleted file mode 100644 index 32a3b01d3..000000000 --- a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * GV11B ECC INTR - * - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include - -#include "fb_intr_ecc_gv11b.h" - -#include - -int gv11b_fb_intr_inject_hubmmu_ecc_error(struct gk20a *g, - struct nvgpu_hw_err_inject_info *err, - u32 error_info) -{ - unsigned int reg_addr = err->get_reg_addr(); - - nvgpu_info(g, "Injecting HUBMMU fault %s", err->name); - nvgpu_writel(g, reg_addr, err->get_reg_val(1U)); - - return 0; -} diff --git a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b_fusa.c index 30fbd32eb..2aaef9686 100644 --- a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b_fusa.c @@ -31,6 +31,18 @@ #include +int gv11b_fb_intr_inject_hubmmu_ecc_error(struct gk20a *g, + struct nvgpu_hw_err_inject_info *err, + u32 error_info) +{ + unsigned int reg_addr = err->get_reg_addr(); + + nvgpu_info(g, "Injecting HUBMMU fault %s", err->name); + nvgpu_writel(g, reg_addr, err->get_reg_val(1U)); + + return 0; +} + static inline u32 l2tlb_ecc_control_r(void) { return fb_mmu_l2tlb_ecc_control_r();