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gpu: nvgpu: vgpu: init ctx buffers for vf driver
VF needs to allocate gr ctx buffers on gr init, since VF will manage the gr ctx. Jira GVSCI-15769 Change-Id: Ifd09e6b09306c0fd36bddc60caa3d0d56f2b29cb Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863434 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Dinesh T <dt@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* copy of this software and associated documentation files (the "Software"),
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@@ -425,7 +425,7 @@ static int nvgpu_gr_init_ctx_state(struct gk20a *g, struct nvgpu_gr *gr)
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return err;
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return err;
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}
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}
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static int gr_init_ctx_bufs(struct gk20a *g, struct nvgpu_gr *gr)
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int nvgpu_gr_init_ctx_bufs(struct gk20a *g, struct nvgpu_gr *gr)
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{
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{
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int err = 0;
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int err = 0;
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@@ -509,7 +509,7 @@ static int gr_init_setup_sw(struct gk20a *g, struct nvgpu_gr *gr)
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}
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}
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#endif
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#endif
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err = gr_init_ctx_bufs(g, gr);
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err = nvgpu_gr_init_ctx_bufs(g, gr);
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if (err != 0) {
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if (err != 0) {
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goto clean_up;
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goto clean_up;
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}
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}
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@@ -1,7 +1,7 @@
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/*
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/*
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* Virtualized GPU Graphics
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* Virtualized GPU Graphics
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*
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*
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* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* copy of this software and associated documentation files (the "Software"),
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@@ -674,6 +674,12 @@ static int vgpu_gr_init_gr_setup_sw(struct gk20a *g)
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}
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}
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#endif
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#endif
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if (nvgpu_is_vf(g)) {
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err = nvgpu_gr_init_ctx_bufs(g, gr);
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if (err) {
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goto clean_up;
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}
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} else {
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err = vgpu_gr_alloc_global_ctx_buffers(g);
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err = vgpu_gr_alloc_global_ctx_buffers(g);
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if (err) {
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if (err) {
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goto clean_up;
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goto clean_up;
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@@ -683,6 +689,7 @@ static int vgpu_gr_init_gr_setup_sw(struct gk20a *g)
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if (gr->gr_ctx_desc == NULL) {
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if (gr->gr_ctx_desc == NULL) {
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goto clean_up;
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goto clean_up;
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}
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}
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}
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#ifdef CONFIG_NVGPU_GRAPHICS
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#ifdef CONFIG_NVGPU_GRAPHICS
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if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
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if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* copy of this software and associated documentation files (the "Software"),
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@@ -156,6 +156,8 @@ int nvgpu_gr_alloc(struct gk20a *g);
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*/
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*/
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void nvgpu_gr_free(struct gk20a *g);
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void nvgpu_gr_free(struct gk20a *g);
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int nvgpu_gr_init_ctx_bufs(struct gk20a *g, struct nvgpu_gr *gr);
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/**
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/**
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* @brief Reset and enable GR engine HW as phase 2 of GR engine
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* @brief Reset and enable GR engine HW as phase 2 of GR engine
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* initialization.
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* initialization.
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