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gpu: nvgpu: vgpu: init ctx buffers for vf driver

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VF needs to allocate gr ctx buffers on gr init, since VF will manage the
gr ctx.

Jira GVSCI-15769

Change-Id: Ifd09e6b09306c0fd36bddc60caa3d0d56f2b29cb
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863434
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Richard Zhao
2023-01-31 17:41:33 -08:00
committed by mobile promotions
parent e5c5fee01e
commit 7cd377568f
3 changed files with 21 additions and 12 deletions
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6
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -425,7 +425,7 @@ static int nvgpu_gr_init_ctx_state(struct gk20a *g, struct nvgpu_gr *gr)
return err;
}
static int gr_init_ctx_bufs(struct gk20a *g, struct nvgpu_gr *gr)
int nvgpu_gr_init_ctx_bufs(struct gk20a *g, struct nvgpu_gr *gr)
{
int err = 0;
@@ -509,7 +509,7 @@ static int gr_init_setup_sw(struct gk20a *g, struct nvgpu_gr *gr)
}
#endif
err = gr_init_ctx_bufs(g, gr);
err = nvgpu_gr_init_ctx_bufs(g, gr);
if (err != 0) {
goto clean_up;
}

9
drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c
View File

@@ -1,7 +1,7 @@
/*
* Virtualized GPU Graphics
*
* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -674,6 +674,12 @@ static int vgpu_gr_init_gr_setup_sw(struct gk20a *g)
}
#endif
if (nvgpu_is_vf(g)) {
err = nvgpu_gr_init_ctx_bufs(g, gr);
if (err) {
goto clean_up;
}
} else {
err = vgpu_gr_alloc_global_ctx_buffers(g);
if (err) {
goto clean_up;
@@ -683,6 +689,7 @@ static int vgpu_gr_init_gr_setup_sw(struct gk20a *g)
if (gr->gr_ctx_desc == NULL) {
goto clean_up;
}
}
#ifdef CONFIG_NVGPU_GRAPHICS
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {

4
drivers/gpu/nvgpu/include/nvgpu/gr/gr.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -156,6 +156,8 @@ int nvgpu_gr_alloc(struct gk20a *g);
*/
void nvgpu_gr_free(struct gk20a *g);
int nvgpu_gr_init_ctx_bufs(struct gk20a *g, struct nvgpu_gr *gr);
/**
* @brief Reset and enable GR engine HW as phase 2 of GR engine
* initialization.