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gpu: nvgpu: Expose logical mask for MIG

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1) Expose logical mask instead of physical mask when MIG is enabled.
   For legacy, NvGpu expose physical mask.
2) Added fb related info in struct nvgpu_gpu_instance().
4) Added utility api to get the logical id for a given local id
   nvgpu_grmgr_get_gr_gpc_logical_id()
5) Added grmgr api to get max_gpc_count
   nvgpu_grmgr_get_max_gpc_count().
5) Added grmgr's fbp api to get num_fbps and its enable masks.
   nvgpu_grmgr_get_num_fbps()
   nvgpu_grmgr_get_fbp_en_mask()
   nvgpu_grmgr_get_fbp_rop_l2_en_mask()
6) Used grmgr's fbp apis in ioctl_ctrl.c
7) Moved fbp_init_support() in nvgpu_early_init()
8) Added nvgpu_assert handling in grmgr.c
9) Added vgpu hal for get_max_gpc_count().

JIRA NVGPU-5656

Change-Id: I90ac2ad99be608001e7d5d754f6242ad26c70cdb
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2538508
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Lakshmanan M
2021-06-02 21:45:15 +05:30
committed by mobile promotions
parent e2d8bdc38d
commit 7d473f4dcc
13 changed files with 181 additions and 13 deletions
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14
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
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@@ -466,8 +466,8 @@ static long gk20a_ctrl_ioctl_gpu_characteristics(
gpu.max_dbg_tsg_timeslice = g->tsg_dbg_timeslice_max_us;
strlcpy(gpu.chipname, g->name, sizeof(gpu.chipname));
gpu.max_fbps_count = nvgpu_fbp_get_max_fbps_count(g->fbp);
gpu.fbp_en_mask = nvgpu_fbp_get_fbp_en_mask(g->fbp);;
gpu.max_fbps_count = nvgpu_grmgr_get_max_fbps_count(g);
gpu.fbp_en_mask = nvgpu_grmgr_get_fbp_en_mask(g, gpu_instance_id);
gpu.max_ltc_per_fbp = g->ops.top.get_max_ltc_per_fbp(g);
gpu.max_lts_per_ltc = g->ops.top.get_max_lts_per_ltc(g);
gpu.num_ltc = nvgpu_ltc_get_ltc_count(g);
@@ -714,12 +714,14 @@ static int gk20a_ctrl_get_tpc_masks(struct gk20a *g, struct nvgpu_gr_config *gr_
}
static int gk20a_ctrl_get_fbp_l2_masks(
struct gk20a *g, struct nvgpu_gpu_get_fbp_l2_masks_args *args)
struct gk20a *g, u32 gpu_instance_id,
struct nvgpu_gpu_get_fbp_l2_masks_args *args)
{
int err = 0;
const u32 fbp_l2_mask_size = sizeof(u32) *
nvgpu_fbp_get_max_fbps_count(g->fbp);
u32 *fbp_rop_l2_en_mask = nvgpu_fbp_get_rop_l2_en_mask(g->fbp);
nvgpu_grmgr_get_max_fbps_count(g);
u32 *fbp_rop_l2_en_mask =
nvgpu_grmgr_get_fbp_rop_l2_en_mask(g, gpu_instance_id);
if (args->mask_buf_size > 0) {
size_t write_size = fbp_l2_mask_size;
@@ -2072,7 +2074,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
(struct nvgpu_gpu_get_tpc_masks_args *)buf);
break;
case NVGPU_GPU_IOCTL_GET_FBP_L2_MASKS:
err = gk20a_ctrl_get_fbp_l2_masks(g,
err = gk20a_ctrl_get_fbp_l2_masks(g, gpu_instance_id,
(struct nvgpu_gpu_get_fbp_l2_masks_args *)buf);
break;
case NVGPU_GPU_IOCTL_OPEN_CHANNEL: