gpu: nvgpu: Expose logical mask for MIG

1) Expose logical mask instead of physical mask when MIG is enabled.
   For legacy, NvGpu expose physical mask.
2) Added fb related info in struct nvgpu_gpu_instance().
4) Added utility api to get the logical id for a given local id
   nvgpu_grmgr_get_gr_gpc_logical_id()
5) Added grmgr api to get max_gpc_count
   nvgpu_grmgr_get_max_gpc_count().
5) Added grmgr's fbp api to get num_fbps and its enable masks.
   nvgpu_grmgr_get_num_fbps()
   nvgpu_grmgr_get_fbp_en_mask()
   nvgpu_grmgr_get_fbp_rop_l2_en_mask()
6) Used grmgr's fbp apis in ioctl_ctrl.c
7) Moved fbp_init_support() in nvgpu_early_init()
8) Added nvgpu_assert handling in grmgr.c
9) Added vgpu hal for get_max_gpc_count().

JIRA NVGPU-5656

Change-Id: I90ac2ad99be608001e7d5d754f6242ad26c70cdb
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2538508
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit

drivers/gpu/nvgpu/common/gr/gr_config.c

@@ -292,14 +292,14 @@ static int gr_config_init_mig_gpcs(struct nvgpu_gr_config *config)
 	struct gk20a *g = config->g;
 	u32 cur_gr_instance = nvgpu_gr_get_cur_instance_id(g);
 
-	config->max_gpc_count = nvgpu_grmgr_get_gr_num_gpcs(g, cur_gr_instance);
+	config->max_gpc_count = nvgpu_grmgr_get_max_gpc_count(g);
 	config->gpc_count = nvgpu_grmgr_get_gr_num_gpcs(g, cur_gr_instance);
 	if (config->gpc_count == 0U) {
 		nvgpu_err(g, "gpc_count==0!");
 		return -EINVAL;
 	}
 
-	config->gpc_mask = nvgpu_grmgr_get_gr_physical_gpc_mask(
+	config->gpc_mask = nvgpu_grmgr_get_gr_logical_gpc_mask(
 		g, cur_gr_instance);
 
 	return 0;

drivers/gpu/nvgpu/common/grmgr/grmgr.c

@@ -29,6 +29,7 @@
 #include <nvgpu/grmgr.h>
 #include <nvgpu/engines.h>
 #include <nvgpu/device.h>
+#include <nvgpu/fbp.h>
 
 int nvgpu_init_gr_manager(struct gk20a *g)
 {
@@ -45,10 +46,13 @@ int nvgpu_init_gr_manager(struct gk20a *g)
 #endif
 
 	/* Number of gpu instance is 1 for legacy mode */
+	g->mig.max_gpc_count = g->ops.top.get_max_gpc_count(g);
+	nvgpu_assert(g->mig.max_gpc_count > 0U);
 	g->mig.gpc_count = g->ops.priv_ring.get_gpc_count(g);
 	nvgpu_assert(g->mig.gpc_count > 0U);
 	g->mig.num_gpu_instances = 1U;
 	g->mig.is_nongr_engine_sharable = false;
+	g->mig.max_fbps_count = nvgpu_fbp_get_max_fbps_count(g->fbp);
 
 	gpu_instance->gpu_instance_id = 0U;
 	gpu_instance->is_memory_partition_supported = false;
@@ -120,22 +124,34 @@ int nvgpu_init_gr_manager(struct gk20a *g)
 	g->mig.recursive_ref_count = 0U;
 	g->mig.cur_tid = -1;
 
+	gpu_instance->fbp_en_mask = nvgpu_fbp_get_fbp_en_mask(g->fbp);
+#ifdef CONFIG_NVGPU_NON_FUSA
+	gpu_instance->num_fbp = nvgpu_fbp_get_num_fbps(g->fbp);
+	gpu_instance->fbp_rop_l2_en_mask = nvgpu_fbp_get_rop_l2_en_mask(g->fbp);
+#endif
+
 	g->mig.current_gr_syspipe_id = NVGPU_MIG_INVALID_GR_SYSPIPE_ID;
 
 	nvgpu_log(g, gpu_dbg_mig,
 		"[Physical device] gpu_instance_id[%u] gr_instance_id[%u] "
-			"gr_syspipe_id[%u] num_gpc[%u] gr_engine_id[%u] "
-			"max_veid_count_per_tsg[%u] veid_start_offset[%u] "
-			"is_memory_partition_support[%d] num_lce[%u] ",
+			"gr_syspipe_id[%u] max_gpc_count[%u] num_gpc[%u] "
+			"gr_engine_id[%u] max_veid_count_per_tsg[%u] "
+			"veid_start_offset[%u] is_memory_partition_support[%d] "
+			"num_lce[%u] max_fbps_count[%u] num_fbp[%u] "
+			"fbp_en_mask [0x%x] ",
 		gpu_instance->gpu_instance_id,
 		gr_syspipe->gr_instance_id,
 		gr_syspipe->gr_syspipe_id,
+		g->mig.max_gpc_count,
 		gr_syspipe->num_gpc,
 		gr_syspipe->gr_dev->engine_id,
 		gr_syspipe->max_veid_count_per_tsg,
 		gr_syspipe->veid_start_offset,
 		gpu_instance->is_memory_partition_supported,
-		gpu_instance->num_lce);
+		gpu_instance->num_lce,
+		g->mig.max_fbps_count,
+		gpu_instance->num_fbp,
+		gpu_instance->fbp_en_mask);
 
 	return 0;
 }
@@ -377,9 +393,37 @@ u32 nvgpu_grmgr_get_gr_gpc_phys_id(struct gk20a *g, u32 gr_instance_id,
 	gpu_instance = &g->mig.gpu_instance[gpu_instance_id];
 	gr_syspipe = &gpu_instance->gr_syspipe;
 
+	nvgpu_assert(gpc_local_id < gr_syspipe->num_gpc);
+
+	nvgpu_log(g, gpu_dbg_mig,
+		"gpu_instance_id[%u] gpc_local_id[%u] physical_id[%u]",
+		gpu_instance_id, gpc_local_id,
+		gr_syspipe->gpcs[gpc_local_id].physical_id);
+
 	return gr_syspipe->gpcs[gpc_local_id].physical_id;
 }
 
+u32 nvgpu_grmgr_get_gr_gpc_logical_id(struct gk20a *g, u32 gr_instance_id,
+		u32 gpc_local_id)
+{
+	struct nvgpu_gpu_instance *gpu_instance;
+	struct nvgpu_gr_syspipe *gr_syspipe;
+	u32 gpu_instance_id = nvgpu_grmgr_get_gpu_instance_id(
+		g, gr_instance_id);
+
+	gpu_instance = &g->mig.gpu_instance[gpu_instance_id];
+	gr_syspipe = &gpu_instance->gr_syspipe;
+
+	nvgpu_assert(gpc_local_id < gr_syspipe->num_gpc);
+
+	nvgpu_log(g, gpu_dbg_mig,
+		"gpu_instance_id[%u] gpc_local_id[%u] logical_id[%u]",
+		gpu_instance_id, gpc_local_id,
+		gr_syspipe->gpcs[gpc_local_id].logical_id);
+
+	return gr_syspipe->gpcs[gpc_local_id].logical_id;
+}
+
 u32 nvgpu_grmgr_get_gr_instance_id(struct gk20a *g, u32 gpu_instance_id)
 {
 	u32 gr_instance_id = 0U;
@@ -579,3 +623,68 @@ u32 nvgpu_grmgr_get_gr_physical_gpc_mask(struct gk20a *g, u32 gr_instance_id)
 
 	return physical_gpc_mask;
 }
+
+u32 nvgpu_grmgr_get_num_fbps(struct gk20a *g, u32 gpu_instance_id)
+{
+	struct nvgpu_gpu_instance *gpu_instance;
+
+	if (gpu_instance_id < g->mig.num_gpu_instances) {
+		gpu_instance = &g->mig.gpu_instance[gpu_instance_id];
+
+		nvgpu_log(g, gpu_dbg_mig,
+			"gpu_instance_id[%u] num_fbp[%u]",
+			gpu_instance_id, gpu_instance->num_fbp);
+
+		return gpu_instance->num_fbp;
+	}
+
+	nvgpu_err(g,
+		"gpu_instance_id[%u] >= num_gpu_instances[%u]",
+		gpu_instance_id, g->mig.num_gpu_instances);
+
+	nvgpu_assert(gpu_instance_id < g->mig.num_gpu_instances);
+
+	return U32_MAX;
+}
+
+u32 nvgpu_grmgr_get_fbp_en_mask(struct gk20a *g, u32 gpu_instance_id)
+{
+	struct nvgpu_gpu_instance *gpu_instance;
+
+	if (gpu_instance_id < g->mig.num_gpu_instances) {
+		gpu_instance = &g->mig.gpu_instance[gpu_instance_id];
+
+		nvgpu_log(g, gpu_dbg_mig,
+			"gpu_instance_id[%u] fbp_en_mask[0x%x]",
+			gpu_instance_id, gpu_instance->fbp_en_mask);
+
+		return gpu_instance->fbp_en_mask;
+	}
+
+	nvgpu_err(g,
+		"gpu_instance_id[%u] >= num_gpu_instances[%u]",
+		gpu_instance_id, g->mig.num_gpu_instances);
+
+	nvgpu_assert(gpu_instance_id < g->mig.num_gpu_instances);
+
+	return U32_MAX;
+}
+
+u32 *nvgpu_grmgr_get_fbp_rop_l2_en_mask(struct gk20a *g, u32 gpu_instance_id)
+{
+	struct nvgpu_gpu_instance *gpu_instance;
+
+	if (gpu_instance_id < g->mig.num_gpu_instances) {
+		gpu_instance = &g->mig.gpu_instance[gpu_instance_id];
+
+		return gpu_instance->fbp_rop_l2_en_mask;
+	}
+
+	nvgpu_err(g,
+		"gpu_instance_id[%u] >= num_gpu_instances[%u]",
+		gpu_instance_id, g->mig.num_gpu_instances);
+
+	nvgpu_assert(gpu_instance_id < g->mig.num_gpu_instances);
+
+	return NULL;
+}

drivers/gpu/nvgpu/common/init/nvgpu_init.c

@@ -643,6 +643,7 @@ static int nvgpu_early_init(struct gk20a *g)
 		NVGPU_INIT_TABLE_ENTRY(g->ops.fifo.reset_enable_hw, NO_FLAG),
 		NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_fb_support, NO_FLAG),
 		NVGPU_INIT_TABLE_ENTRY(g->ops.ltc.init_ltc_support, NO_FLAG),
+		NVGPU_INIT_TABLE_ENTRY(g->ops.fbp.fbp_init_support, NO_FLAG),
 		NVGPU_INIT_TABLE_ENTRY(g->ops.grmgr.init_gr_manager, NO_FLAG),
 	};
 
@@ -800,7 +801,6 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 #ifdef CONFIG_NVGPU_LS_PMU
 		NVGPU_INIT_TABLE_ENTRY(g->ops.pmu.pmu_rtos_init, NO_FLAG),
 #endif
-		NVGPU_INIT_TABLE_ENTRY(g->ops.fbp.fbp_init_support, NO_FLAG),
 		NVGPU_INIT_TABLE_ENTRY(g->ops.gr.gr_init_support, NO_FLAG),
 		/**
 		 * All units requiring ECC stats must initialize ECC counters

drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c

@@ -1535,6 +1535,13 @@ int vgpu_gr_set_preemption_mode(struct nvgpu_channel *ch,
 	return err;
 }
 
+u32 vgpu_gr_get_max_gpc_count(struct gk20a *g)
+{
+	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
+
+	return priv->constants.max_gpc_count;
+}
+
 u32 vgpu_gr_get_gpc_count(struct gk20a *g)
 {
 	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);

drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h

@@ -92,6 +92,7 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info);
 void vgpu_gr_handle_sm_esr_event(struct gk20a *g,
 			struct tegra_vgpu_sm_esr_info *info);
 int vgpu_init_gr_support(struct gk20a *g);
+u32 vgpu_gr_get_max_gpc_count(struct gk20a *g);
 u32 vgpu_gr_get_gpc_count(struct gk20a *g);
 u32 vgpu_gr_get_gpc_mask(struct gk20a *g);
 #ifdef CONFIG_NVGPU_DEBUGGER

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c

@@ -1009,6 +1009,7 @@ static const struct gops_fuse vgpu_gv11b_ops_fuse = {
 };
 
 static const struct gops_top vgpu_gv11b_ops_top = {
+	.get_max_gpc_count = vgpu_gr_get_max_gpc_count,
 	.get_max_fbps_count = vgpu_gr_get_max_fbps_count,
 	.get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
 	.get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,

drivers/gpu/nvgpu/include/nvgpu/grmgr.h

@@ -41,6 +41,8 @@ u32 nvgpu_grmgr_get_gr_syspipe_id(struct gk20a *g, u32 gr_instance_id);
 u32 nvgpu_grmgr_get_gr_num_gpcs(struct gk20a *g, u32 gr_instance_id);
 u32 nvgpu_grmgr_get_gr_gpc_phys_id(struct gk20a *g, u32 gr_instance_id,
 		u32 gpc_local_id);
+u32 nvgpu_grmgr_get_gr_gpc_logical_id(struct gk20a *g, u32 gr_instance_id,
+		u32 gpc_local_id);
 u32 nvgpu_grmgr_get_gr_instance_id(struct gk20a *g, u32 gpu_instance_id);
 bool nvgpu_grmgr_is_valid_runlist_id(struct gk20a *g,
 		u32 gpu_instance_id, u32 runlist_id);
@@ -53,6 +55,9 @@ u32 nvgpu_grmgr_get_gpu_instance_max_veid_count(struct gk20a *g,
 u32 nvgpu_grmgr_get_gr_max_veid_count(struct gk20a *g, u32 gr_instance_id);
 u32 nvgpu_grmgr_get_gr_logical_gpc_mask(struct gk20a *g, u32 gr_instance_id);
 u32 nvgpu_grmgr_get_gr_physical_gpc_mask(struct gk20a *g, u32 gr_instance_id);
+u32 nvgpu_grmgr_get_num_fbps(struct gk20a *g, u32 gpu_instance_id);
+u32 nvgpu_grmgr_get_fbp_en_mask(struct gk20a *g, u32 gpu_instance_id);
+u32 *nvgpu_grmgr_get_fbp_rop_l2_en_mask(struct gk20a *g, u32 gpu_instance_id);
 
 static inline bool nvgpu_grmgr_is_mig_type_gpu_instance(
 		struct nvgpu_gpu_instance *gpu_instance)
@@ -66,4 +71,14 @@ static inline bool nvgpu_grmgr_is_multi_gr_enabled(struct gk20a *g)
 		(g->mig.num_gpu_instances > 1U));
 }
 
+static inline u32 nvgpu_grmgr_get_max_gpc_count(struct gk20a *g)
+{
+	return g->mig.max_gpc_count;
+}
+
+static inline u32 nvgpu_grmgr_get_max_fbps_count(struct gk20a *g)
+{
+	return g->mig.max_fbps_count;
+}
+
 #endif /* NVGPU_GRMGR_H */

drivers/gpu/nvgpu/include/nvgpu/mig.h

@@ -110,6 +110,21 @@ struct nvgpu_gpu_instance {
 	struct nvgpu_gr_syspipe gr_syspipe;
 	/** Number of Logical CE engine associated to this gpu instances. */
 	u32 num_lce;
+	/** Number of Logical FBP associated to this gpu instances. */
+	u32 num_fbp;
+	/**
+	 * Mask of FBPs. A set bit indicates FBP is available, otherwise
+	 * it is not available.
+	 * For Legacy, it is represent physical FBP mask.
+	 * For MIG, it is represent logical FBP mask.
+	 */
+	u32 fbp_en_mask;
+	/**
+	 * Array to hold physical masks of LTCs per FBP.
+	 * For Legacy, array is indexed by FBP physical index.
+	 * For MIG, array is indexed by FBP logical index.
+	 */
+	u32 *fbp_rop_l2_en_mask;
 	/** Memory area to store h/w CE engine ids. */
 	const struct nvgpu_device *lce_devs[NVGPU_MIG_MAX_ENGINES];
 	/* Flag to indicate whether memory partition is supported or not. */
@@ -183,6 +198,10 @@ struct nvgpu_mig {
 	u32 usable_gr_syspipe_mask;
 	/** Array of usable GR sys pipe instance id. */
 	u32 usable_gr_syspipe_instance_id[NVGPU_MIG_MAX_ENGINES];
+	/**
+	 * Max possible number of GPCs in GR engines.
+	 */
+	u32 max_gpc_count;
 	/** Total Number of GPCs (priv_ring enumerated (floor swept) value). */
 	u32 gpc_count;
 	/** GPC count associated to each GPC group. */
@@ -191,6 +210,8 @@ struct nvgpu_mig {
 	u32 num_gpu_instances;
 	/** Maximum gr sys pipes are supported by HW. */
 	u32 max_gr_sys_pipes_supported;
+	/** Maximum fbps are supported by HW. */
+	u32 max_fbps_count;
 	/** Total number of enabled gr syspipes count. */
 	u32 num_gr_sys_pipes_enabled;
 	/** GR sys pipe enabled mask. */

drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c

@@ -466,8 +466,8 @@ static long gk20a_ctrl_ioctl_gpu_characteristics(
 	gpu.max_dbg_tsg_timeslice = g->tsg_dbg_timeslice_max_us;
 
 	strlcpy(gpu.chipname, g->name, sizeof(gpu.chipname));
-	gpu.max_fbps_count = nvgpu_fbp_get_max_fbps_count(g->fbp);
-	gpu.fbp_en_mask = nvgpu_fbp_get_fbp_en_mask(g->fbp);;
+	gpu.max_fbps_count = nvgpu_grmgr_get_max_fbps_count(g);
+	gpu.fbp_en_mask = nvgpu_grmgr_get_fbp_en_mask(g, gpu_instance_id);
 	gpu.max_ltc_per_fbp =  g->ops.top.get_max_ltc_per_fbp(g);
 	gpu.max_lts_per_ltc = g->ops.top.get_max_lts_per_ltc(g);
 	gpu.num_ltc = nvgpu_ltc_get_ltc_count(g);
@@ -714,12 +714,14 @@ static int gk20a_ctrl_get_tpc_masks(struct gk20a *g, struct nvgpu_gr_config *gr_
 }
 
 static int gk20a_ctrl_get_fbp_l2_masks(
-	struct gk20a *g, struct nvgpu_gpu_get_fbp_l2_masks_args *args)
+	struct gk20a *g, u32 gpu_instance_id,
+	struct nvgpu_gpu_get_fbp_l2_masks_args *args)
 {
 	int err = 0;
 	const u32 fbp_l2_mask_size = sizeof(u32) *
-			nvgpu_fbp_get_max_fbps_count(g->fbp);
-	u32 *fbp_rop_l2_en_mask = nvgpu_fbp_get_rop_l2_en_mask(g->fbp);
+			nvgpu_grmgr_get_max_fbps_count(g);
+	u32 *fbp_rop_l2_en_mask =
+		nvgpu_grmgr_get_fbp_rop_l2_en_mask(g, gpu_instance_id);
 
 	if (args->mask_buf_size > 0) {
 		size_t write_size = fbp_l2_mask_size;
@@ -2072,7 +2074,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
 			(struct nvgpu_gpu_get_tpc_masks_args *)buf);
 		break;
 	case NVGPU_GPU_IOCTL_GET_FBP_L2_MASKS:
-		err = gk20a_ctrl_get_fbp_l2_masks(g,
+		err = gk20a_ctrl_get_fbp_l2_masks(g, gpu_instance_id,
 			(struct nvgpu_gpu_get_fbp_l2_masks_args *)buf);
 		break;
 	case NVGPU_GPU_IOCTL_OPEN_CHANNEL:

userspace/units/acr/nvgpu-acr.c

@@ -179,10 +179,13 @@ static void nvgpu_init_gr_manager(struct gk20a *g)
 	struct nvgpu_gpu_instance *gpu_instance = &g->mig.gpu_instance[0];
 	struct nvgpu_gr_syspipe *gr_syspipe = &gpu_instance->gr_syspipe;
 
+	g->mig.max_gpc_count = 1;
+	g->mig.gpc_count = 1;
 	g->mig.num_gpu_instances = 1;
 	g->mig.num_gr_sys_pipes_enabled = 1;
 	gr_syspipe->gr_instance_id = 0U;
 	gr_syspipe->gr_syspipe_id = 0U;
+	gr_syspipe->num_gpc = 1;
 }
 
 static int init_acr_falcon_test_env(struct unit_module *m, struct gk20a *g)

userspace/units/gr/nvgpu-gr.c

@@ -48,10 +48,13 @@ static void nvgpu_init_gr_manager(struct gk20a *g)
 	struct nvgpu_gpu_instance *gpu_instance = &g->mig.gpu_instance[0];
 	struct nvgpu_gr_syspipe *gr_syspipe = &gpu_instance->gr_syspipe;
 
+	g->mig.max_gpc_count = 1;
+	g->mig.gpc_count = 1;
 	g->mig.num_gpu_instances = 1;
 	g->mig.num_gr_sys_pipes_enabled = 1;
 	gr_syspipe->gr_instance_id = 0U;
 	gr_syspipe->gr_syspipe_id = 0U;
+	gr_syspipe->num_gpc = 1;
 }
 
 int test_gr_init_setup(struct unit_module *m, struct gk20a *g, void *args)

userspace/units/ltc/nvgpu-ltc.c

@@ -270,10 +270,13 @@ static void nvgpu_init_gr_manager(struct gk20a *g)
 	struct nvgpu_gpu_instance *gpu_instance = &g->mig.gpu_instance[0];
 	struct nvgpu_gr_syspipe *gr_syspipe = &gpu_instance->gr_syspipe;
 
+	g->mig.max_gpc_count = 1;
+	g->mig.gpc_count = 1;
 	g->mig.num_gpu_instances = 1;
 	g->mig.num_gr_sys_pipes_enabled = 1;
 	gr_syspipe->gr_instance_id = 0U;
 	gr_syspipe->gr_syspipe_id = 0U;
+	gr_syspipe->num_gpc = 1;
 }
 
 int test_ltc_ecc_init_free(struct unit_module *m, struct gk20a *g, void *args)

userspace/units/pmu/nvgpu-pmu.c

@@ -167,10 +167,13 @@ static void nvgpu_init_gr_manager(struct gk20a *g)
 	struct nvgpu_gpu_instance *gpu_instance = &g->mig.gpu_instance[0];
 	struct nvgpu_gr_syspipe *gr_syspipe = &gpu_instance->gr_syspipe;
 
+	g->mig.max_gpc_count = 1;
+	g->mig.gpc_count = 1;
 	g->mig.num_gpu_instances = 1;
 	g->mig.num_gr_sys_pipes_enabled = 1;
 	gr_syspipe->gr_instance_id = 0U;
 	gr_syspipe->gr_syspipe_id = 0U;
+	gr_syspipe->num_gpc = 1;
 }
 
 static int init_pmu_falcon_test_env(struct unit_module *m, struct gk20a *g)