diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c
index 74f07ba69..4bc4bd0c5 100644
--- a/drivers/gpu/nvgpu/common/gr/gr.c
+++ b/drivers/gpu/nvgpu/common/gr/gr.c
@@ -473,7 +473,7 @@ clean_up:
 static int gr_init_reset_enable_hw(struct gk20a *g)
 {
 	struct netlist_av_list *sw_non_ctx_load =
-			&g->netlist_vars->sw_non_ctx_load;
+		nvgpu_netlist_get_sw_non_ctx_load_av_list(g);
 	u32 i;
 	int err = 0;
 
diff --git a/drivers/gpu/nvgpu/common/gr/gr_falcon.c b/drivers/gpu/nvgpu/common/gr/gr_falcon.c
index 60c000042..4db639181 100644
--- a/drivers/gpu/nvgpu/common/gr/gr_falcon.c
+++ b/drivers/gpu/nvgpu/common/gr/gr_falcon.c
@@ -303,12 +303,12 @@ int nvgpu_gr_falcon_init_ctxsw_ucode(struct gk20a *g,
 	ucode_size = 0;
 	nvgpu_gr_falcon_init_ctxsw_ucode_segments(&ucode_info->fecs,
 		&ucode_size, fecs_boot_desc,
-		g->netlist_vars->ucode.fecs.inst.count * (u32)sizeof(u32),
-		g->netlist_vars->ucode.fecs.data.count * (u32)sizeof(u32));
+		nvgpu_netlist_get_fecs_inst_count(g) * (u32)sizeof(u32),
+		nvgpu_netlist_get_fecs_data_count(g) * (u32)sizeof(u32));
 	nvgpu_gr_falcon_init_ctxsw_ucode_segments(&ucode_info->gpccs,
 		&ucode_size, gpccs_boot_desc,
-		g->netlist_vars->ucode.gpccs.inst.count * (u32)sizeof(u32),
-		g->netlist_vars->ucode.gpccs.data.count * (u32)sizeof(u32));
+		nvgpu_netlist_get_gpccs_inst_count(g) * (u32)sizeof(u32),
+		nvgpu_netlist_get_gpccs_data_count(g) * (u32)sizeof(u32));
 
 	err = nvgpu_dma_alloc_sys(g, ucode_size, &ucode_info->surface_desc);
 	if (err != 0) {
@@ -318,8 +318,8 @@ int nvgpu_gr_falcon_init_ctxsw_ucode(struct gk20a *g,
 	nvgpu_gr_falcon_copy_ctxsw_ucode_segments(g, &ucode_info->surface_desc,
 		&ucode_info->fecs,
 		fecs_boot_image,
-		g->netlist_vars->ucode.fecs.inst.l,
-		g->netlist_vars->ucode.fecs.data.l);
+		nvgpu_netlist_get_fecs_inst_list(g),
+		nvgpu_netlist_get_fecs_data_list(g));
 
 	nvgpu_release_firmware(g, fecs_fw);
 	fecs_fw = NULL;
@@ -327,8 +327,8 @@ int nvgpu_gr_falcon_init_ctxsw_ucode(struct gk20a *g,
 	nvgpu_gr_falcon_copy_ctxsw_ucode_segments(g, &ucode_info->surface_desc,
 		&ucode_info->gpccs,
 		gpccs_boot_image,
-		g->netlist_vars->ucode.gpccs.inst.l,
-		g->netlist_vars->ucode.gpccs.data.l);
+		nvgpu_netlist_get_gpccs_inst_list(g),
+		nvgpu_netlist_get_gpccs_data_list(g));
 
 	nvgpu_release_firmware(g, gpccs_fw);
 	gpccs_fw = NULL;
@@ -362,12 +362,12 @@ static void nvgpu_gr_falcon_load_dmem(struct gk20a *g)
 
 	nvgpu_log_fn(g, " ");
 
-	ucode_u32_size = g->netlist_vars->ucode.gpccs.data.count;
-	ucode_u32_data = (const u32 *)g->netlist_vars->ucode.gpccs.data.l;
+	ucode_u32_size = nvgpu_netlist_get_gpccs_data_count(g);
+	ucode_u32_data = (const u32 *)nvgpu_netlist_get_gpccs_data_list(g);
 	g->ops.gr.falcon.load_gpccs_dmem(g, ucode_u32_data, ucode_u32_size);
 
-	ucode_u32_size = g->netlist_vars->ucode.fecs.data.count;
-	ucode_u32_data = (const u32 *)g->netlist_vars->ucode.fecs.data.l;
+	ucode_u32_size = nvgpu_netlist_get_fecs_data_count(g);
+	ucode_u32_data = (const u32 *)nvgpu_netlist_get_fecs_data_list(g);
 	g->ops.gr.falcon.load_fecs_dmem(g, ucode_u32_data, ucode_u32_size);
 
 	nvgpu_log_fn(g, "done");
@@ -380,13 +380,13 @@ static void nvgpu_gr_falcon_load_imem(struct gk20a *g)
 
 	nvgpu_log_fn(g, " ");
 
-	ucode_u32_size = g->netlist_vars->ucode.gpccs.inst.count;
-	ucode_u32_data = (const u32 *)g->netlist_vars->ucode.gpccs.inst.l;
+	ucode_u32_size = nvgpu_netlist_get_gpccs_inst_count(g);
+	ucode_u32_data = (const u32 *)nvgpu_netlist_get_gpccs_inst_list(g);
 	g->ops.gr.falcon.load_gpccs_imem(g, ucode_u32_data, ucode_u32_size);
 
 
-	ucode_u32_size = g->netlist_vars->ucode.fecs.inst.count;
-	ucode_u32_data = (const u32 *)g->netlist_vars->ucode.fecs.inst.l;
+	ucode_u32_size = nvgpu_netlist_get_fecs_inst_count(g);
+	ucode_u32_data = (const u32 *)nvgpu_netlist_get_fecs_inst_list(g);
 	g->ops.gr.falcon.load_fecs_imem(g, ucode_u32_data, ucode_u32_size);
 
 	nvgpu_log_fn(g, "done");
diff --git a/drivers/gpu/nvgpu/common/gr/hwpm_map.c b/drivers/gpu/nvgpu/common/gr/hwpm_map.c
index e550f97aa..687fb6e28 100644
--- a/drivers/gpu/nvgpu/common/gr/hwpm_map.c
+++ b/drivers/gpu/nvgpu/common/gr/hwpm_map.c
@@ -238,7 +238,7 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g,
 		num_tpcs = nvgpu_gr_config_get_gpc_tpc_count(g->gr.config, gpc_num);
 		base = gpc_base + (gpc_stride * gpc_num) + tpc_in_gpc_base;
 		if (add_ctxsw_buffer_map_entries_subunits(map,
-					&g->netlist_vars->ctxsw_regs.pm_tpc,
+					nvgpu_netlist_get_pm_tpc_ctxsw_regs(g),
 					count, offset, max_cnt, base,
 					num_tpcs, ~U32(0U), tpc_in_gpc_stride,
 					(tpc_in_gpc_stride - 1U)) != 0) {
@@ -248,7 +248,7 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g,
 		num_ppcs = nvgpu_gr_config_get_gpc_ppc_count(g->gr.config, gpc_num);
 		base = gpc_base + (gpc_stride * gpc_num) + ppc_in_gpc_base;
 		if (add_ctxsw_buffer_map_entries_subunits(map,
-					&g->netlist_vars->ctxsw_regs.pm_ppc,
+					nvgpu_netlist_get_pm_ppc_ctxsw_regs(g),
 					count, offset, max_cnt, base, num_ppcs,
 					~U32(0U), ppc_in_gpc_stride,
 					(ppc_in_gpc_stride - 1U)) != 0) {
@@ -257,7 +257,7 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g,
 
 		base = gpc_base + (gpc_stride * gpc_num);
 		if (add_ctxsw_buffer_map_entries_pmgpc(g, map,
-					&g->netlist_vars->ctxsw_regs.pm_gpc,
+					nvgpu_netlist_get_pm_gpc_ctxsw_regs(g),
 					count, offset, max_cnt, base,
 					(gpc_stride - 1U)) != 0) {
 			return -EINVAL;
@@ -265,31 +265,31 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g,
 
 		base = NV_XBAR_MXBAR_PRI_GPC_GNIC_STRIDE * gpc_num;
 		if (add_ctxsw_buffer_map_entries(map,
-					&g->netlist_vars->ctxsw_regs.pm_ucgpc,
-					count, offset, max_cnt, base, ~U32(0U)) != 0) {
+				nvgpu_netlist_get_pm_ucgpc_ctxsw_regs(g),
+				count, offset, max_cnt, base, ~U32(0U)) != 0) {
 			return -EINVAL;
 		}
 
 		base = (g->ops.perf.get_pmm_per_chiplet_offset() * gpc_num);
 		if (add_ctxsw_buffer_map_entries(map,
-					&g->netlist_vars->ctxsw_regs.perf_gpc,
-					count, offset, max_cnt, base, ~U32(0U)) != 0) {
+				nvgpu_netlist_get_perf_gpc_ctxsw_regs(g),
+				count, offset, max_cnt, base, ~U32(0U)) != 0) {
 			return -EINVAL;
 		}
 
 		base = (NV_PERF_PMMGPCROUTER_STRIDE * gpc_num);
 		if (add_ctxsw_buffer_map_entries(map,
-					&g->netlist_vars->ctxsw_regs.gpc_router,
-					count, offset, max_cnt, base, ~U32(0U)) != 0) {
+				nvgpu_netlist_get_gpc_router_ctxsw_regs(g),
+				count, offset, max_cnt, base, ~U32(0U)) != 0) {
 			return -EINVAL;
 		}
 
 		/* Counter Aggregation Unit, if available */
-		if (g->netlist_vars->ctxsw_regs.pm_cau.count != 0U) {
+		if (nvgpu_netlist_get_pm_cau_ctxsw_regs(g)->count != 0U) {
 			base = gpc_base + (gpc_stride * gpc_num)
 					+ tpc_in_gpc_base;
 			if (add_ctxsw_buffer_map_entries_subunits(map,
-					&g->netlist_vars->ctxsw_regs.pm_cau,
+					nvgpu_netlist_get_pm_cau_ctxsw_regs(g),
 					count, offset, max_cnt, base, num_tpcs,
 					~U32(0U), tpc_in_gpc_stride,
 					(tpc_in_gpc_stride - 1U)) != 0) {
@@ -399,20 +399,23 @@ static int nvgpu_gr_hwpm_map_create(struct gk20a *g,
 	}
 
 	/* Add entries from _LIST_pm_ctx_reg_SYS */
-	if (add_ctxsw_buffer_map_entries_pmsys(map, &g->netlist_vars->ctxsw_regs.pm_sys,
-				&count, &offset, hwpm_ctxsw_reg_count_max, 0, ~U32(0U)) != 0) {
+	if (add_ctxsw_buffer_map_entries_pmsys(map,
+		nvgpu_netlist_get_pm_sys_ctxsw_regs(g),
+		&count, &offset, hwpm_ctxsw_reg_count_max, 0, ~U32(0U)) != 0) {
 		goto cleanup;
 	}
 
 	/* Add entries from _LIST_nv_perf_ctx_reg_SYS */
-	if (add_ctxsw_buffer_map_entries(map, &g->netlist_vars->ctxsw_regs.perf_sys,
-				&count, &offset, hwpm_ctxsw_reg_count_max, 0, ~U32(0U)) != 0) {
+	if (add_ctxsw_buffer_map_entries(map,
+		nvgpu_netlist_get_perf_sys_ctxsw_regs(g),
+		&count, &offset, hwpm_ctxsw_reg_count_max, 0, ~U32(0U)) != 0) {
 		goto cleanup;
 	}
 
 	/* Add entries from _LIST_nv_perf_sysrouter_ctx_reg*/
-	if (add_ctxsw_buffer_map_entries(map, &g->netlist_vars->ctxsw_regs.perf_sys_router,
-				&count, &offset, hwpm_ctxsw_reg_count_max, 0, ~U32(0U)) != 0) {
+	if (add_ctxsw_buffer_map_entries(map,
+		nvgpu_netlist_get_perf_sys_router_ctxsw_regs(g),
+		&count, &offset, hwpm_ctxsw_reg_count_max, 0, ~U32(0U)) != 0) {
 		goto cleanup;
 	}
 
@@ -422,7 +425,7 @@ static int nvgpu_gr_hwpm_map_create(struct gk20a *g,
 
 	/* Add entries from _LIST_nv_perf_pma_ctx_reg*/
 	ret = add_ctxsw_buffer_map_entries(map,
-			&g->netlist_vars->ctxsw_regs.perf_pma, &count, &offset,
+		nvgpu_netlist_get_perf_pma_ctxsw_regs(g), &count, &offset,
 			hwpm_ctxsw_reg_count_max, 0, ~U32(0U));
 	if (ret != 0) {
 		goto cleanup;
@@ -432,7 +435,7 @@ static int nvgpu_gr_hwpm_map_create(struct gk20a *g,
 
 	/* Add entries from _LIST_nv_perf_fbp_ctx_regs */
 	if (add_ctxsw_buffer_map_entries_subunits(map,
-			&g->netlist_vars->ctxsw_regs.fbp, &count, &offset,
+		nvgpu_netlist_get_fbp_ctxsw_regs(g), &count, &offset,
 			hwpm_ctxsw_reg_count_max, 0, g->gr.num_fbps, ~U32(0U),
 			g->ops.perf.get_pmm_per_chiplet_offset(),
 			~U32(0U)) != 0) {
@@ -441,7 +444,7 @@ static int nvgpu_gr_hwpm_map_create(struct gk20a *g,
 
 	/* Add entries from _LIST_nv_perf_fbprouter_ctx_regs */
 	if (add_ctxsw_buffer_map_entries_subunits(map,
-			&g->netlist_vars->ctxsw_regs.fbp_router,
+			nvgpu_netlist_get_fbp_router_ctxsw_regs(g),
 			&count, &offset, hwpm_ctxsw_reg_count_max, 0,
 			g->gr.num_fbps, ~U32(0U), NV_PERF_PMM_FBP_ROUTER_STRIDE,
 			~U32(0U)) != 0) {
@@ -456,7 +459,7 @@ static int nvgpu_gr_hwpm_map_create(struct gk20a *g,
 
 	/* Add entries from _LIST_nv_pm_fbpa_ctx_regs */
 	if (add_ctxsw_buffer_map_entries_subunits(map,
-			&g->netlist_vars->ctxsw_regs.pm_fbpa,
+			nvgpu_netlist_get_pm_fbpa_ctxsw_regs(g),
 			&count, &offset, hwpm_ctxsw_reg_count_max, 0,
 			num_fbpas, active_fbpa_mask, fbpa_stride, ~U32(0U))
 				!= 0) {
@@ -465,14 +468,14 @@ static int nvgpu_gr_hwpm_map_create(struct gk20a *g,
 
 	/* Add entries from _LIST_nv_pm_rop_ctx_regs */
 	if (add_ctxsw_buffer_map_entries(map,
-			&g->netlist_vars->ctxsw_regs.pm_rop, &count, &offset,
+		nvgpu_netlist_get_pm_rop_ctxsw_regs(g), &count, &offset,
 			hwpm_ctxsw_reg_count_max, 0, ~U32(0U)) != 0) {
 		goto cleanup;
 	}
 
 	/* Add entries from _LIST_compressed_nv_pm_ltc_ctx_regs */
 	if (add_ctxsw_buffer_map_entries_subunits(map,
-			&g->netlist_vars->ctxsw_regs.pm_ltc, &count, &offset,
+			nvgpu_netlist_get_pm_ltc_ctxsw_regs(g), &count, &offset,
 			hwpm_ctxsw_reg_count_max, 0, num_ltc, ~U32(0U),
 			ltc_stride, ~U32(0U)) != 0) {
 		goto cleanup;
diff --git a/drivers/gpu/nvgpu/common/gr/obj_ctx.c b/drivers/gpu/nvgpu/common/gr/obj_ctx.c
index d0d58ec34..7fd62779f 100644
--- a/drivers/gpu/nvgpu/common/gr/obj_ctx.c
+++ b/drivers/gpu/nvgpu/common/gr/obj_ctx.c
@@ -336,11 +336,11 @@ int nvgpu_gr_obj_ctx_commit_global_ctx_buffers(struct gk20a *g,
 static int nvgpu_gr_obj_ctx_alloc_sw_bundle(struct gk20a *g)
 {
 	struct netlist_av_list *sw_bundle_init =
-			&g->netlist_vars->sw_bundle_init;
+			nvgpu_netlist_get_sw_bundle_init_av_list(g);
 	struct netlist_av_list *sw_veid_bundle_init =
-			&g->netlist_vars->sw_veid_bundle_init;
+			nvgpu_netlist_get_sw_veid_bundle_init_av_list(g);
 	struct netlist_av64_list *sw_bundle64_init =
-			&g->netlist_vars->sw_bundle64_init;
+			nvgpu_netlist_get_sw_bundle64_init_av64_list(g);
 	int err = 0;
 
 	/* enable pipe mode override */
@@ -396,8 +396,10 @@ int nvgpu_gr_obj_ctx_alloc_golden_ctx_image(struct gk20a *g,
 	u64 size;
 	struct nvgpu_mem *gr_mem;
 	int err = 0;
-	struct netlist_aiv_list *sw_ctx_load = &g->netlist_vars->sw_ctx_load;
-	struct netlist_av_list *sw_method_init = &g->netlist_vars->sw_method_init;
+	struct netlist_aiv_list *sw_ctx_load =
+				nvgpu_netlist_get_sw_ctx_load_aiv_list(g);
+	struct netlist_av_list *sw_method_init =
+				nvgpu_netlist_get_sw_method_init_av_list(g);
 	u32 data;
 
 	nvgpu_log_fn(g, " ");
diff --git a/drivers/gpu/nvgpu/common/netlist/netlist.c b/drivers/gpu/nvgpu/common/netlist/netlist.c
index 584dac730..d885b6f1c 100644
--- a/drivers/gpu/nvgpu/common/netlist/netlist.c
+++ b/drivers/gpu/nvgpu/common/netlist/netlist.c
@@ -30,13 +30,15 @@
 #include <nvgpu/netlist.h>
 #include <nvgpu/string.h>
 
-struct netlist_av *nvgpu_netlist_alloc_av_list(struct gk20a *g, struct netlist_av_list *avl)
+struct netlist_av *nvgpu_netlist_alloc_av_list(struct gk20a *g,
+						struct netlist_av_list *avl)
 {
 	avl->l = nvgpu_kzalloc(g, avl->count * sizeof(*avl->l));
 	return avl->l;
 }
 
-struct netlist_av64 *nvgpu_netlist_alloc_av64_list(struct gk20a *g, struct netlist_av64_list *avl)
+struct netlist_av64 *nvgpu_netlist_alloc_av64_list(struct gk20a *g,
+						struct netlist_av64_list *avl)
 {
 	avl->l = nvgpu_kzalloc(g, avl->count * sizeof(*avl->l));
 	return avl->l;
@@ -49,7 +51,8 @@ struct netlist_aiv *nvgpu_netlist_alloc_aiv_list(struct gk20a *g,
 	return aivl->l;
 }
 
-u32 *nvgpu_netlist_alloc_u32_list(struct gk20a *g, struct netlist_u32_list *u32l)
+u32 *nvgpu_netlist_alloc_u32_list(struct gk20a *g,
+					struct netlist_u32_list *u32l)
 {
 	u32l->l = nvgpu_kzalloc(g, u32l->count * sizeof(*u32l->l));
 	return u32l->l;
@@ -551,3 +554,192 @@ void nvgpu_netlist_deinit_ctx_vars(struct gk20a *g)
 	nvgpu_kfree(g, netlist_vars);
 	g->netlist_vars = NULL;
 }
+
+struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_load_av_list(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->sw_non_ctx_load;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_sw_ctx_load_aiv_list(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->sw_ctx_load;
+}
+
+struct netlist_av_list *nvgpu_netlist_get_sw_method_init_av_list(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->sw_method_init;
+}
+
+struct netlist_av_list *nvgpu_netlist_get_sw_bundle_init_av_list(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->sw_bundle_init;
+}
+
+struct netlist_av_list *nvgpu_netlist_get_sw_veid_bundle_init_av_list(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->sw_veid_bundle_init;
+}
+
+struct netlist_av64_list *nvgpu_netlist_get_sw_bundle64_init_av64_list(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->sw_bundle64_init;
+}
+
+u32 nvgpu_netlist_get_fecs_inst_count(struct gk20a *g)
+{
+	return g->netlist_vars->ucode.fecs.inst.count;
+}
+
+u32 nvgpu_netlist_get_fecs_data_count(struct gk20a *g)
+{
+	return g->netlist_vars->ucode.fecs.data.count;
+}
+
+u32 nvgpu_netlist_get_gpccs_inst_count(struct gk20a *g)
+{
+	return g->netlist_vars->ucode.gpccs.inst.count;
+}
+
+u32 nvgpu_netlist_get_gpccs_data_count(struct gk20a *g)
+{
+	return g->netlist_vars->ucode.gpccs.data.count;
+}
+
+u32 *nvgpu_netlist_get_fecs_inst_list(struct gk20a *g)
+{
+	return g->netlist_vars->ucode.fecs.inst.l;
+}
+
+u32 *nvgpu_netlist_get_fecs_data_list(struct gk20a *g)
+{
+	return g->netlist_vars->ucode.fecs.data.l;
+}
+
+u32 *nvgpu_netlist_get_gpccs_inst_list(struct gk20a *g)
+{
+	return g->netlist_vars->ucode.gpccs.inst.l;
+}
+
+u32 *nvgpu_netlist_get_gpccs_data_list(struct gk20a *g)
+{
+	return g->netlist_vars->ucode.gpccs.data.l;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_sys_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.sys;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_gpc_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.gpc;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_tpc_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.tpc;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_zcull_gpc_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.zcull_gpc;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_ppc_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.ppc;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_pm_sys_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.pm_sys;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_pm_gpc_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.pm_gpc;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_pm_tpc_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.pm_tpc;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_pm_ppc_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.pm_ppc;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_perf_sys_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.perf_sys;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_perf_gpc_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.perf_gpc;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_fbp_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.fbp;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_fbp_router_ctxsw_regs(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.fbp_router;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_gpc_router_ctxsw_regs(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.gpc_router;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_pm_ltc_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.pm_ltc;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_pm_fbpa_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.pm_fbpa;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_perf_sys_router_ctxsw_regs(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.perf_sys_router;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_perf_pma_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.perf_pma;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_pm_rop_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.pm_rop;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_pm_ucgpc_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.pm_ucgpc;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_etpc_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.etpc;
+}
+
+struct netlist_aiv_list *nvgpu_netlist_get_pm_cau_ctxsw_regs(struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.pm_cau;
+}
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index c71ae0ca5..96383d347 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -1488,6 +1488,7 @@ gr_gk20a_process_context_buffer_priv_segment(struct gk20a *g,
 	u32 address, base_address;
 	u32 sys_offset, gpc_offset, tpc_offset, ppc_offset;
 	u32 ppc_num, tpc_num, tpc_addr, gpc_addr, ppc_addr;
+	struct netlist_aiv_list *list;
 	struct netlist_aiv *reg;
 	u32 gpc_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_BASE);
 	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
@@ -1505,8 +1506,9 @@ gr_gk20a_process_context_buffer_priv_segment(struct gk20a *g,
 	/* Process the SYS/BE segment. */
 	if ((addr_type == CTXSW_ADDR_TYPE_SYS) ||
 	    (addr_type == CTXSW_ADDR_TYPE_BE)) {
-		for (i = 0; i < g->netlist_vars->ctxsw_regs.sys.count; i++) {
-			reg = &g->netlist_vars->ctxsw_regs.sys.l[i];
+		list = nvgpu_netlist_get_sys_ctxsw_regs(g);
+		for (i = 0; i < list->count; i++) {
+			reg = &list->l[i];
 			address    = reg->addr;
 			sys_offset = reg->index;
 
@@ -1520,8 +1522,9 @@ gr_gk20a_process_context_buffer_priv_segment(struct gk20a *g,
 	/* Process the TPC segment. */
 	if (addr_type == CTXSW_ADDR_TYPE_TPC) {
 		for (tpc_num = 0; tpc_num < num_tpcs; tpc_num++) {
-			for (i = 0; i < g->netlist_vars->ctxsw_regs.tpc.count; i++) {
-				reg = &g->netlist_vars->ctxsw_regs.tpc.l[i];
+			list = nvgpu_netlist_get_tpc_ctxsw_regs(g);
+			for (i = 0; i < list->count; i++) {
+				reg = &list->l[i];
 				address = reg->addr;
 				tpc_addr = pri_tpccs_addr_mask(address);
 				base_address = gpc_base +
@@ -1550,8 +1553,9 @@ gr_gk20a_process_context_buffer_priv_segment(struct gk20a *g,
 		}
 
 		for (tpc_num = 0; tpc_num < num_tpcs; tpc_num++) {
-			for (i = 0; i < g->netlist_vars->ctxsw_regs.etpc.count; i++) {
-				reg = &g->netlist_vars->ctxsw_regs.etpc.l[i];
+			list = nvgpu_netlist_get_etpc_ctxsw_regs(g);
+			for (i = 0; i < list->count; i++) {
+				reg = &list->l[i];
 				address = reg->addr;
 				tpc_addr = pri_tpccs_addr_mask(address);
 				base_address = g->ops.gr.get_egpc_base(g) +
@@ -1583,8 +1587,9 @@ gr_gk20a_process_context_buffer_priv_segment(struct gk20a *g,
 	/* Process the PPC segment. */
 	if (addr_type == CTXSW_ADDR_TYPE_PPC) {
 		for (ppc_num = 0; ppc_num < num_ppcs; ppc_num++) {
-			for (i = 0; i < g->netlist_vars->ctxsw_regs.ppc.count; i++) {
-				reg = &g->netlist_vars->ctxsw_regs.ppc.l[i];
+			list = nvgpu_netlist_get_ppc_ctxsw_regs(g);
+			for (i = 0; i < list->count; i++) {
+				reg = &list->l[i];
 				address = reg->addr;
 				ppc_addr = pri_ppccs_addr_mask(address);
 				base_address = gpc_base +
@@ -1611,8 +1616,9 @@ gr_gk20a_process_context_buffer_priv_segment(struct gk20a *g,
 
 	/* Process the GPC segment. */
 	if (addr_type == CTXSW_ADDR_TYPE_GPC) {
-		for (i = 0; i < g->netlist_vars->ctxsw_regs.gpc.count; i++) {
-			reg = &g->netlist_vars->ctxsw_regs.gpc.l[i];
+		list = nvgpu_netlist_get_gpc_ctxsw_regs(g);
+		for (i = 0; i < list->count; i++) {
+			reg = &list->l[i];
 
 			address = reg->addr;
 			gpc_addr = pri_gpccs_addr_mask(address);
@@ -1642,13 +1648,13 @@ static int gr_gk20a_determine_ppc_configuration(struct gk20a *g,
 	 * in the GPC reglist, so we can't error out if ppc.count == 0
 	 */
 	if ((!g->netlist_valid) ||
-	    ((g->netlist_vars->ctxsw_regs.ppc.count == 0U) &&
+	    ((nvgpu_netlist_get_ppc_ctxsw_regs(g)->count == 0U) &&
 	     (num_pes_per_gpc > 1U))) {
 		return -EINVAL;
 	}
 
 	g->ops.gr.ctxsw_prog.get_ppc_info(context, num_ppcs, ppc_mask);
-	*reg_ppc_count = g->netlist_vars->ctxsw_regs.ppc.count;
+	*reg_ppc_count = nvgpu_netlist_get_ppc_ctxsw_regs(g)->count;
 
 	return 0;
 }
@@ -1661,17 +1667,17 @@ int gr_gk20a_get_offset_in_gpccs_segment(struct gk20a *g,
 					u32 *__offset_in_segment)
 {
 	u32 offset_in_segment = 0;
+	u32 tpc_count = nvgpu_netlist_get_tpc_ctxsw_regs(g)->count;
+	u32 etpc_count = nvgpu_netlist_get_etpc_ctxsw_regs(g)->count;
 
 	if (addr_type == CTXSW_ADDR_TYPE_TPC) {
 		/*
-		 * reg = g->netlist_vars->ctxsw_regs.tpc.l;
+		 * reg = nvgpu_netlist_get_tpc_ctxsw_regs(g)->l;
 		 * offset_in_segment = 0;
 		 */
 	} else if ((addr_type == CTXSW_ADDR_TYPE_EGPC) ||
 			(addr_type == CTXSW_ADDR_TYPE_ETPC)) {
-		offset_in_segment =
-			((g->netlist_vars->ctxsw_regs.tpc.count *
-				num_tpcs) << 2);
+		offset_in_segment = ((tpc_count * num_tpcs) << 2);
 
 		nvgpu_log(g, gpu_dbg_info | gpu_dbg_gpu_dbg,
 			"egpc etpc offset_in_segment 0x%#08x",
@@ -1682,9 +1688,7 @@ int gr_gk20a_get_offset_in_gpccs_segment(struct gk20a *g,
 		 * Advance offset past TPC data to PPC data.
 		 */
 		offset_in_segment =
-			(((g->netlist_vars->ctxsw_regs.tpc.count +
-				g->netlist_vars->ctxsw_regs.etpc.count) *
-			  num_tpcs) << 2);
+			(((tpc_count + etpc_count) * num_tpcs) << 2);
 	} else if (addr_type == CTXSW_ADDR_TYPE_GPC) {
 		/*
 		 * The ucode stores TPC/PPC data before GPC data.
@@ -1696,15 +1700,11 @@ int gr_gk20a_get_offset_in_gpccs_segment(struct gk20a *g,
 				GPU_LIT_NUM_PES_PER_GPC);
 		if (num_pes_per_gpc > 1U) {
 			offset_in_segment =
-				((((g->netlist_vars->ctxsw_regs.tpc.count +
-					g->netlist_vars->ctxsw_regs.etpc.count) *
-					num_tpcs) << 2) +
+				((((tpc_count + etpc_count) * num_tpcs) << 2) +
 					((reg_list_ppc_count * num_ppcs) << 2));
 		} else {
 			offset_in_segment =
-				(((g->netlist_vars->ctxsw_regs.tpc.count +
-					g->netlist_vars->ctxsw_regs.etpc.count) *
-					num_tpcs) << 2);
+				(((tpc_count + etpc_count) * num_tpcs) << 2);
 		}
 	} else {
 		nvgpu_log_fn(g, "Unknown address type.");
diff --git a/drivers/gpu/nvgpu/include/nvgpu/netlist.h b/drivers/gpu/nvgpu/include/nvgpu/netlist.h
index 45e9804ec..672d7634d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/netlist.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/netlist.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -212,4 +212,53 @@ int nvgpu_netlist_init_ctx_vars(struct gk20a *g);
 int nvgpu_netlist_init_ctx_vars_sim(struct gk20a *g);
 void nvgpu_netlist_deinit_ctx_vars(struct gk20a *g);
 
+struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_load_av_list(
+							struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_sw_ctx_load_aiv_list(
+							struct gk20a *g);
+struct netlist_av_list *nvgpu_netlist_get_sw_method_init_av_list(
+							struct gk20a *g);
+struct netlist_av_list *nvgpu_netlist_get_sw_bundle_init_av_list(
+							struct gk20a *g);
+struct netlist_av_list *nvgpu_netlist_get_sw_veid_bundle_init_av_list(
+							struct gk20a *g);
+struct netlist_av64_list *nvgpu_netlist_get_sw_bundle64_init_av64_list(
+							struct gk20a *g);
+
+u32 nvgpu_netlist_get_fecs_inst_count(struct gk20a *g);
+u32 nvgpu_netlist_get_fecs_data_count(struct gk20a *g);
+u32 nvgpu_netlist_get_gpccs_inst_count(struct gk20a *g);
+u32 nvgpu_netlist_get_gpccs_data_count(struct gk20a *g);
+u32 *nvgpu_netlist_get_fecs_inst_list(struct gk20a *g);
+u32 *nvgpu_netlist_get_fecs_data_list(struct gk20a *g);
+u32 *nvgpu_netlist_get_gpccs_inst_list(struct gk20a *g);
+u32 *nvgpu_netlist_get_gpccs_data_list(struct gk20a *g);
+
+struct netlist_aiv_list *nvgpu_netlist_get_sys_ctxsw_regs(struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_gpc_ctxsw_regs(struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_tpc_ctxsw_regs(struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_zcull_gpc_ctxsw_regs(
+							struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_ppc_ctxsw_regs(struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_pm_sys_ctxsw_regs(struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_pm_gpc_ctxsw_regs(struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_pm_tpc_ctxsw_regs(struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_pm_ppc_ctxsw_regs(struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_perf_sys_ctxsw_regs(struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_perf_gpc_ctxsw_regs(struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_fbp_ctxsw_regs(struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_fbp_router_ctxsw_regs(
+							struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_gpc_router_ctxsw_regs(
+							struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_pm_ltc_ctxsw_regs(struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_pm_fbpa_ctxsw_regs(struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_perf_sys_router_ctxsw_regs(
+							struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_perf_pma_ctxsw_regs(struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_pm_rop_ctxsw_regs(struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_pm_ucgpc_ctxsw_regs(struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_etpc_ctxsw_regs(struct gk20a *g);
+struct netlist_aiv_list *nvgpu_netlist_get_pm_cau_ctxsw_regs(struct gk20a *g);
+
 #endif /* NVGPU_NETLIST_H */
diff --git a/drivers/gpu/nvgpu/tu104/gr_tu104.c b/drivers/gpu/nvgpu/tu104/gr_tu104.c
index cfc564ff4..c4824488c 100644
--- a/drivers/gpu/nvgpu/tu104/gr_tu104.c
+++ b/drivers/gpu/nvgpu/tu104/gr_tu104.c
@@ -54,10 +54,12 @@ int gr_tu104_get_offset_in_gpccs_segment(struct gk20a *g,
 	u32 offset_in_segment = 0;
 	u32 num_pes_per_gpc = nvgpu_get_litter_value(g,
 				GPU_LIT_NUM_PES_PER_GPC);
+	u32 tpc_count = nvgpu_netlist_get_tpc_ctxsw_regs(g)->count;
+	u32 gpc_count = nvgpu_netlist_get_gpc_ctxsw_regs(g)->count;
 
 	if (addr_type == CTXSW_ADDR_TYPE_TPC) {
 		/*
-		 * reg = g->netlist_vars->ctxsw_regs.tpc.l;
+		 * reg = nvgpu_netlist_get_tpc_ctxsw_regs(g)->l;
 		 * offset_in_segment = 0;
 		 */
 	} else if (addr_type == CTXSW_ADDR_TYPE_PPC) {
@@ -65,9 +67,7 @@ int gr_tu104_get_offset_in_gpccs_segment(struct gk20a *g,
 		 * The ucode stores TPC data before PPC data.
 		 * Advance offset past TPC data to PPC data.
 		 */
-		offset_in_segment =
-			((g->netlist_vars->ctxsw_regs.tpc.count *
-				num_tpcs) << 2);
+		offset_in_segment = ((tpc_count * num_tpcs) << 2);
 	} else if (addr_type == CTXSW_ADDR_TYPE_GPC) {
 		/*
 		 * The ucode stores TPC/PPC data before GPC data.
@@ -76,28 +76,22 @@ int gr_tu104_get_offset_in_gpccs_segment(struct gk20a *g,
 		 * Note 1 PES_PER_GPC case
 		 */
 		if (num_pes_per_gpc > 1U) {
-			offset_in_segment =
-				(((g->netlist_vars->ctxsw_regs.tpc.count *
-					num_tpcs) << 2) +
+			offset_in_segment = (((tpc_count * num_tpcs) << 2) +
 				((reg_list_ppc_count * num_ppcs) << 2));
 		} else {
-			offset_in_segment =
-				((g->netlist_vars->ctxsw_regs.tpc.count *
-					num_tpcs) << 2);
+			offset_in_segment = ((tpc_count * num_tpcs) << 2);
 		}
 	} else if ((addr_type == CTXSW_ADDR_TYPE_EGPC) ||
 			(addr_type == CTXSW_ADDR_TYPE_ETPC)) {
 		if (num_pes_per_gpc > 1U) {
 			offset_in_segment =
-				((g->netlist_vars->ctxsw_regs.tpc.count *
-					num_tpcs) << 2) +
+				((tpc_count * num_tpcs) << 2) +
 				((reg_list_ppc_count * num_ppcs) << 2) +
-				(g->netlist_vars->ctxsw_regs.gpc.count << 2);
+							(gpc_count << 2);
 		} else {
 			offset_in_segment =
-				((g->netlist_vars->ctxsw_regs.tpc.count *
-					num_tpcs) << 2) +
-				(g->netlist_vars->ctxsw_regs.gpc.count << 2);
+				((tpc_count * num_tpcs) << 2) +
+							(gpc_count << 2);
 		}
 
 		/* aligned to next 256 byte */