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gpu: nvgpu: add perfmon Hals

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Add following HALs for Ga100 and Ga10b. These will
be used for calculating chiplet offsets corresponding
to GPC/FBP perf register.

get_pmmgpcrouter_per_chiplet_offset
get_pmmfbprouter_per_chiplet_offset

get_hwpm_fbp_perfmon_regs_base
get_hwpm_gpc_perfmon_regs_base
get_hwpm_fbprouter_perfmon_regs_base
get_hwpm_gpcrouter_perfmon_regs_base

Bug 200712091

Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: Iec1a16ef4a3c26dca054c30d95bef991983dc2b7
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2648832
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Debarshi Dutta
2022-01-06 15:59:25 +05:30
committed by mobile promotions
parent 3d01b89e68
commit 7db5f0d339
7 changed files with 81 additions and 4 deletions
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45
drivers/gpu/nvgpu/hal/perf/perf_ga10b.c
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -471,6 +471,18 @@ u32 ga10b_perf_get_pmmgpc_per_chiplet_offset(void)
return (perf_pmmgpc_extent_v() - perf_pmmgpc_base_v() + reg_offset);
}
u32 ga10b_perf_get_pmmgpcrouter_per_chiplet_offset(void)
{
/*
* No register to find the offset of pmmgpc register.
* Difference of pmmgpc register address ranges plus 1 will provide
* the offset
*/
u32 reg_offset = 1U;
return (perf_pmmgpcrouter_extent_v() - perf_pmmgpcrouter_base_v() + reg_offset);
}
u32 ga10b_perf_get_pmmfbp_per_chiplet_offset(void)
{
/*
@@ -483,6 +495,37 @@ u32 ga10b_perf_get_pmmfbp_per_chiplet_offset(void)
return (perf_pmmfbp_extent_v() - perf_pmmfbp_base_v() + reg_offset);
}
u32 ga10b_perf_get_pmmfbprouter_per_chiplet_offset(void)
{
/*
* No register to find the offset of pmmgpc register.
* Difference of pmmgpc register address ranges plus 1 will provide
* the offset
*/
u32 reg_offset = 1U;
return (perf_pmmfbprouter_extent_v() - perf_pmmfbprouter_base_v() + reg_offset);
}
u32 ga10b_get_hwpm_fbp_perfmon_regs_base(struct gk20a *g)
{
return perf_pmmfbp_base_v();
}
u32 ga10b_get_hwpm_gpc_perfmon_regs_base(struct gk20a *g)
{
return perf_pmmgpc_base_v();
}
u32 ga10b_get_hwpm_fbprouter_perfmon_regs_base(struct gk20a *g)
{
return perf_pmmfbprouter_base_v();
}
u32 ga10b_get_hwpm_gpcrouter_perfmon_regs_base(struct gk20a *g)
{
return perf_pmmgpcrouter_base_v();
}
void ga10b_perf_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon,
u32 *num_fbp_perfmon, u32 *num_gpc_perfmon)
{