gpu: nvgpu: add perfmon Hals

Add following HALs for Ga100 and Ga10b. These will
be used for calculating chiplet offsets corresponding
to GPC/FBP perf register.

get_pmmgpcrouter_per_chiplet_offset
get_pmmfbprouter_per_chiplet_offset

get_hwpm_fbp_perfmon_regs_base
get_hwpm_gpc_perfmon_regs_base
get_hwpm_fbprouter_perfmon_regs_base
get_hwpm_gpcrouter_perfmon_regs_base

Bug 200712091

Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: Iec1a16ef4a3c26dca054c30d95bef991983dc2b7
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2648832
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/grmgr/grmgr.c

@@ -459,6 +459,17 @@ u32 nvgpu_grmgr_get_gr_num_gpcs(struct gk20a *g, u32 gr_instance_id)
 	return gr_syspipe->num_gpc;
 }
 
+u32 nvgpu_grmgr_get_gr_num_fbps(struct gk20a *g, u32 gr_instance_id)
+{
+	struct nvgpu_gpu_instance *gpu_instance;
+	u32 gpu_instance_id = nvgpu_grmgr_get_gpu_instance_id(
+		g, gr_instance_id);
+
+	gpu_instance = &g->mig.gpu_instance[gpu_instance_id];
+
+	return gpu_instance->num_fbp;
+}
+
 u32 nvgpu_grmgr_get_gr_gpc_phys_id(struct gk20a *g, u32 gr_instance_id,
 		u32 gpc_local_id)
 {

drivers/gpu/nvgpu/hal/init/hal_ga100.c

@@ -1474,7 +1474,13 @@ static const struct gops_perf ga100_ops_perf = {
 	.get_pmmsys_per_chiplet_offset = ga100_perf_get_pmmsys_per_chiplet_offset,
 	.get_pmmgpc_per_chiplet_offset = ga100_perf_get_pmmgpc_per_chiplet_offset,
 	.get_pmmfbp_per_chiplet_offset = ga100_perf_get_pmmfbp_per_chiplet_offset,
+	.get_pmmgpcrouter_per_chiplet_offset = ga10b_perf_get_pmmgpcrouter_per_chiplet_offset,
+	.get_pmmfbprouter_per_chiplet_offset = ga10b_perf_get_pmmfbprouter_per_chiplet_offset,
 	.update_get_put = ga10b_perf_update_get_put,
+	.get_hwpm_fbp_perfmon_regs_base = ga10b_get_hwpm_fbp_perfmon_regs_base,
+	.get_hwpm_gpc_perfmon_regs_base = ga10b_get_hwpm_gpc_perfmon_regs_base,
+	.get_hwpm_fbprouter_perfmon_regs_base = ga10b_get_hwpm_fbprouter_perfmon_regs_base,
+	.get_hwpm_gpcrouter_perfmon_regs_base = ga10b_get_hwpm_gpcrouter_perfmon_regs_base,
 	.get_hwpm_sys_perfmon_regs = ga100_perf_get_hwpm_sys_perfmon_regs,
 	.get_hwpm_gpc_perfmon_regs = ga100_perf_get_hwpm_gpc_perfmon_regs,
 	.get_hwpm_fbp_perfmon_regs = ga100_perf_get_hwpm_fbp_perfmon_regs,

drivers/gpu/nvgpu/hal/init/hal_ga10b.c

@@ -1491,11 +1491,14 @@ static const struct gops_perf ga10b_ops_perf = {
 	.get_membuf_overflow_status = ga10b_perf_get_membuf_overflow_status,
 	.get_pmmsys_per_chiplet_offset = ga10b_perf_get_pmmsys_per_chiplet_offset,
 	.get_pmmgpc_per_chiplet_offset = ga10b_perf_get_pmmgpc_per_chiplet_offset,
+	.get_pmmgpcrouter_per_chiplet_offset = ga10b_perf_get_pmmgpcrouter_per_chiplet_offset,
 	.get_pmmfbp_per_chiplet_offset = ga10b_perf_get_pmmfbp_per_chiplet_offset,
+	.get_pmmfbprouter_per_chiplet_offset = ga10b_perf_get_pmmfbprouter_per_chiplet_offset,
 	.update_get_put = ga10b_perf_update_get_put,
 	.get_hwpm_sys_perfmon_regs = ga10b_perf_get_hwpm_sys_perfmon_regs,
 	.get_hwpm_gpc_perfmon_regs = ga10b_perf_get_hwpm_gpc_perfmon_regs,
 	.get_hwpm_fbp_perfmon_regs = ga10b_perf_get_hwpm_fbp_perfmon_regs,
+	.get_hwpm_gpcrouter_perfmon_regs_base = ga10b_get_hwpm_gpcrouter_perfmon_regs_base,
 	.set_pmm_register = gv11b_perf_set_pmm_register,
 	.get_num_hwpm_perfmon = ga10b_perf_get_num_hwpm_perfmon,
 	.init_hwpm_pmm_register = ga10b_perf_init_hwpm_pmm_register,

drivers/gpu/nvgpu/hal/perf/perf_ga10b.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -471,6 +471,18 @@ u32 ga10b_perf_get_pmmgpc_per_chiplet_offset(void)
 	return (perf_pmmgpc_extent_v() - perf_pmmgpc_base_v() + reg_offset);
 }
 
+u32 ga10b_perf_get_pmmgpcrouter_per_chiplet_offset(void)
+{
+	/*
+	 * No register to find the offset of pmmgpc register.
+	 * Difference of pmmgpc register address ranges plus 1 will provide
+	 * the offset
+	 */
+	u32 reg_offset = 1U;
+
+	return (perf_pmmgpcrouter_extent_v() - perf_pmmgpcrouter_base_v() + reg_offset);
+}
+
 u32 ga10b_perf_get_pmmfbp_per_chiplet_offset(void)
 {
 	/*
@@ -483,6 +495,37 @@ u32 ga10b_perf_get_pmmfbp_per_chiplet_offset(void)
 	return (perf_pmmfbp_extent_v() - perf_pmmfbp_base_v() + reg_offset);
 }
 
+u32 ga10b_perf_get_pmmfbprouter_per_chiplet_offset(void)
+{
+	/*
+	 * No register to find the offset of pmmgpc register.
+	 * Difference of pmmgpc register address ranges plus 1 will provide
+	 * the offset
+	 */
+	u32 reg_offset = 1U;
+
+	return (perf_pmmfbprouter_extent_v() - perf_pmmfbprouter_base_v() + reg_offset);
+}
+
+u32 ga10b_get_hwpm_fbp_perfmon_regs_base(struct gk20a *g)
+{
+	return perf_pmmfbp_base_v();
+}
+u32 ga10b_get_hwpm_gpc_perfmon_regs_base(struct gk20a *g)
+{
+	return perf_pmmgpc_base_v();
+}
+
+u32 ga10b_get_hwpm_fbprouter_perfmon_regs_base(struct gk20a *g)
+{
+	return perf_pmmfbprouter_base_v();
+}
+
+u32 ga10b_get_hwpm_gpcrouter_perfmon_regs_base(struct gk20a *g)
+{
+	return perf_pmmgpcrouter_base_v();
+}
+
 void ga10b_perf_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon,
 				u32 *num_fbp_perfmon, u32 *num_gpc_perfmon)
 {

drivers/gpu/nvgpu/hal/perf/perf_ga10b.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -47,11 +47,18 @@ void ga10b_perf_deinit_inst_block(struct gk20a *g);
 u32 ga10b_perf_get_pmmsys_per_chiplet_offset(void);
 u32 ga10b_perf_get_pmmgpc_per_chiplet_offset(void);
 u32 ga10b_perf_get_pmmfbp_per_chiplet_offset(void);
+u32 ga10b_perf_get_pmmgpcrouter_per_chiplet_offset(void);
+u32 ga10b_perf_get_pmmfbprouter_per_chiplet_offset(void);
 
 const u32 *ga10b_perf_get_hwpm_sys_perfmon_regs(u32 *count);
 const u32 *ga10b_perf_get_hwpm_gpc_perfmon_regs(u32 *count);
 const u32 *ga10b_perf_get_hwpm_fbp_perfmon_regs(u32 *count);
 
+u32 ga10b_get_hwpm_fbp_perfmon_regs_base(struct gk20a *g);
+u32 ga10b_get_hwpm_gpc_perfmon_regs_base(struct gk20a *g);
+u32 ga10b_get_hwpm_fbprouter_perfmon_regs_base(struct gk20a *g);
+u32 ga10b_get_hwpm_gpcrouter_perfmon_regs_base(struct gk20a *g);
+
 void ga10b_perf_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon,
 		u32 *num_fbp_perfmon, u32 *num_gpc_perfmon);
 void ga10b_perf_init_hwpm_pmm_register(struct gk20a *g);

drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -85,12 +85,18 @@ struct gops_perf {
 	bool (*get_membuf_overflow_status)(struct gk20a *g);
 	u32 (*get_pmmsys_per_chiplet_offset)(void);
 	u32 (*get_pmmgpc_per_chiplet_offset)(void);
+	u32 (*get_pmmgpcrouter_per_chiplet_offset)(void);
+	u32 (*get_pmmfbprouter_per_chiplet_offset)(void);
 	u32 (*get_pmmfbp_per_chiplet_offset)(void);
 	int (*update_get_put)(struct gk20a *g, u64 bytes_consumed,
 		bool update_available_bytes, u64 *put_ptr, bool *overflowed);
 	const u32 *(*get_hwpm_sys_perfmon_regs)(u32 *count);
 	const u32 *(*get_hwpm_fbp_perfmon_regs)(u32 *count);
 	const u32 *(*get_hwpm_gpc_perfmon_regs)(u32 *count);
+	u32 (*get_hwpm_fbp_perfmon_regs_base)(struct gk20a *g);
+	u32 (*get_hwpm_gpc_perfmon_regs_base)(struct gk20a *g);
+	u32 (*get_hwpm_fbprouter_perfmon_regs_base)(struct gk20a *g);
+	u32 (*get_hwpm_gpcrouter_perfmon_regs_base)(struct gk20a *g);
 	void (*init_hwpm_pmm_register)(struct gk20a *g);
 	void (*get_num_hwpm_perfmon)(struct gk20a *g, u32 *num_sys_perfmon,
 				     u32 *num_fbp_perfmon,

drivers/gpu/nvgpu/include/nvgpu/grmgr.h

@@ -1,7 +1,7 @@
 /*
  * GR MANAGER
  *
- * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -48,6 +48,7 @@ int nvgpu_grmgr_config_gr_remap_window(struct gk20a *g,
 u32 nvgpu_grmgr_get_num_gr_instances(struct gk20a *g);
 u32 nvgpu_grmgr_get_gr_syspipe_id(struct gk20a *g, u32 gr_instance_id);
 u32 nvgpu_grmgr_get_gr_num_gpcs(struct gk20a *g, u32 gr_instance_id);
+u32 nvgpu_grmgr_get_gr_num_fbps(struct gk20a *g, u32 gr_instance_id);
 u32 nvgpu_grmgr_get_gr_gpc_phys_id(struct gk20a *g, u32 gr_instance_id,
 		u32 gpc_local_id);
 u32 nvgpu_grmgr_get_gr_gpc_logical_id(struct gk20a *g, u32 gr_instance_id,