diff --git a/drivers/gpu/nvgpu/common/gr/gr_config.c b/drivers/gpu/nvgpu/common/gr/gr_config.c
index 0b164fb53..0c7b7eac6 100644
--- a/drivers/gpu/nvgpu/common/gr/gr_config.c
+++ b/drivers/gpu/nvgpu/common/gr/gr_config.c
@@ -299,7 +299,8 @@ static int gr_config_init_mig_gpcs(struct nvgpu_gr_config *config)
 		return -EINVAL;
 	}
 
-	config->gpc_mask = nvgpu_safe_sub_u32(BIT32(config->gpc_count), 1U);
+	config->gpc_mask = nvgpu_grmgr_get_gr_physical_gpc_mask(
+		g, cur_gr_instance);
 
 	return 0;
 }
diff --git a/drivers/gpu/nvgpu/common/grmgr/grmgr.c b/drivers/gpu/nvgpu/common/grmgr/grmgr.c
index 4555e198f..99e9649c1 100644
--- a/drivers/gpu/nvgpu/common/grmgr/grmgr.c
+++ b/drivers/gpu/nvgpu/common/grmgr/grmgr.c
@@ -533,3 +533,30 @@ u32 nvgpu_grmgr_get_gr_logical_gpc_mask(struct gk20a *g, u32 gr_instance_id)
 
 	return logical_gpc_mask;
 }
+
+u32 nvgpu_grmgr_get_gr_physical_gpc_mask(struct gk20a *g, u32 gr_instance_id)
+{
+	u32 physical_gpc_mask = 0U;
+	u32 gpc_indx;
+	struct nvgpu_gpu_instance *gpu_instance;
+	struct nvgpu_gr_syspipe *gr_syspipe;
+	u32 gpu_instance_id = nvgpu_grmgr_get_gpu_instance_id(
+		g, gr_instance_id);
+
+	gpu_instance = &g->mig.gpu_instance[gpu_instance_id];
+	gr_syspipe = &gpu_instance->gr_syspipe;
+
+	for (gpc_indx = 0U; gpc_indx < gr_syspipe->num_gpc; gpc_indx++) {
+		physical_gpc_mask |= BIT32(
+			gr_syspipe->gpcs[gpc_indx].physical_id);
+
+		nvgpu_log(g, gpu_dbg_mig,
+			"gpu_instance_id[%u] gr_instance_id[%u] gpc_indx[%u] "
+				"physical_id[%u] physical_gpc_mask[%x]",
+			gpu_instance_id, gr_instance_id, gpc_indx,
+			gr_syspipe->gpcs[gpc_indx].physical_id,
+			physical_gpc_mask);
+	}
+
+	return physical_gpc_mask;
+}
diff --git a/drivers/gpu/nvgpu/include/nvgpu/grmgr.h b/drivers/gpu/nvgpu/include/nvgpu/grmgr.h
index b65072e39..4d39e4950 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/grmgr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/grmgr.h
@@ -52,6 +52,7 @@ u32 nvgpu_grmgr_get_gpu_instance_max_veid_count(struct gk20a *g,
 		u32 gpu_instance_id);
 u32 nvgpu_grmgr_get_gr_max_veid_count(struct gk20a *g, u32 gr_instance_id);
 u32 nvgpu_grmgr_get_gr_logical_gpc_mask(struct gk20a *g, u32 gr_instance_id);
+u32 nvgpu_grmgr_get_gr_physical_gpc_mask(struct gk20a *g, u32 gr_instance_id);
 
 static inline bool nvgpu_grmgr_is_mig_type_gpu_instance(
 		struct nvgpu_gpu_instance *gpu_instance)