From 7df16ee9c4f983fcf49032d6b1e7ff18ef0074fd Mon Sep 17 00:00:00 2001 From: mpoojary Date: Sun, 13 Mar 2022 04:02:39 +0000 Subject: [PATCH] gpu: nvgpu: Add support for acr safety binaries Add support to pick ACR safety binaries when in safety for ga10b Jira NVGPU-8108 Change-Id: I3aca5e9d4b6e90af87cc7d8520366304ab579ec3 Signed-off-by: mpoojary Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2680710 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.c | 43 +++++++++++++++++++-- 1 file changed, 39 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.c b/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.c index f4dde171b..fdafb0b98 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.c +++ b/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.c @@ -50,6 +50,14 @@ #define GSPPROD_RISCV_ACR_FW_CODE "acr-gsp.text.encrypt.bin.prod" #define GSPPROD_RISCV_ACR_FW_DATA "acr-gsp.data.encrypt.bin.prod" +#define GSPDBG_RISCV_ACR_FW_SAFETY_MANIFEST "acr-gsp-safety.manifest.encrypt.bin.out.bin" +#define GSPDBG_RISCV_ACR_FW_SAFETY_CODE "acr-gsp-safety.text.encrypt.bin" +#define GSPDBG_RISCV_ACR_FW_SAFETY_DATA "acr-gsp-safety.data.encrypt.bin" + +#define GSPPROD_RISCV_ACR_FW_SAFETY_MANIFEST "acr-gsp-safety.manifest.encrypt.bin.out.bin.prod" +#define GSPPROD_RISCV_ACR_FW_SAFETY_CODE "acr-gsp-safety.text.encrypt.bin.prod" +#define GSPPROD_RISCV_ACR_FW_SAFETY_DATA "acr-gsp-safety.data.encrypt.bin.prod" + static int ga10b_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr) { int err = 0; @@ -299,12 +307,25 @@ static u32 ga10b_acr_lsf_config(struct gk20a *g, return lsf_enable_mask; } -static void ga10b_acr_default_sw_init(struct gk20a *g, struct hs_acr *riscv_hs) +#ifndef CONFIG_NVGPU_NON_FUSA +static void ga10b_acr_safety_ucode_select(struct gk20a *g, + struct hs_acr *riscv_hs) { - nvgpu_log_fn(g, " "); - - riscv_hs->acr_type = ACR_DEFAULT; + if (g->ops.pmu.is_debug_mode_enabled(g)) { + riscv_hs->acr_code_name = GSPDBG_RISCV_ACR_FW_SAFETY_CODE; + riscv_hs->acr_data_name = GSPDBG_RISCV_ACR_FW_SAFETY_DATA; + riscv_hs->acr_manifest_name = GSPDBG_RISCV_ACR_FW_SAFETY_MANIFEST; + } else { + riscv_hs->acr_code_name = GSPPROD_RISCV_ACR_FW_SAFETY_CODE; + riscv_hs->acr_data_name = GSPPROD_RISCV_ACR_FW_SAFETY_DATA; + riscv_hs->acr_manifest_name = GSPPROD_RISCV_ACR_FW_SAFETY_MANIFEST; + } +} +#else +static void ga10b_acr_non_safety_ucode_select(struct gk20a *g, + struct hs_acr *riscv_hs) +{ if (g->ops.pmu.is_debug_mode_enabled(g)) { riscv_hs->acr_code_name = GSPDBG_RISCV_ACR_FW_CODE; riscv_hs->acr_data_name = GSPDBG_RISCV_ACR_FW_DATA; @@ -314,6 +335,20 @@ static void ga10b_acr_default_sw_init(struct gk20a *g, struct hs_acr *riscv_hs) riscv_hs->acr_data_name = GSPPROD_RISCV_ACR_FW_DATA; riscv_hs->acr_manifest_name = GSPPROD_RISCV_ACR_FW_MANIFEST; } +} +#endif + +static void ga10b_acr_default_sw_init(struct gk20a *g, struct hs_acr *riscv_hs) +{ + nvgpu_log_fn(g, " "); + + riscv_hs->acr_type = ACR_DEFAULT; + +#ifndef CONFIG_NVGPU_NON_FUSA + ga10b_acr_safety_ucode_select(g, riscv_hs); +#else + ga10b_acr_non_safety_ucode_select(g, riscv_hs); +#endif riscv_hs->acr_flcn = &g->gsp_flcn; riscv_hs->report_acr_engine_bus_err_status =