gpu: nvgpu: cleanup gr_priv header include

Add new common gr functions
nvgpu_gr_remove_support
nvgpu_gr_sw_ready
nvgpu_gr_override_ecc_val
These functions help to avoid gr_priv.h include outside some gr files.

Jira NVGPU-3218

Change-Id: I5d59a61b8b8c63c29a0b2407b961fb57f8e400bd
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107700
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-04-26 16:19:17 -07:00
committed by mobile promotions
parent e22c4cbbec
commit 7e396a7e9f
4 changed files with 27 additions and 7 deletions

View File

@@ -784,3 +784,20 @@ int nvgpu_gr_halt_pipe(struct gk20a *g)
return g->ops.gr.falcon.ctrl_ctxsw(g, return g->ops.gr.falcon.ctrl_ctxsw(g,
NVGPU_GR_FALCON_METHOD_HALT_PIPELINE, 0U, NULL); NVGPU_GR_FALCON_METHOD_HALT_PIPELINE, 0U, NULL);
} }
void nvgpu_gr_remove_support(struct gk20a *g)
{
if (g->gr->remove_support != NULL) {
g->gr->remove_support(g);
}
}
void nvgpu_gr_sw_ready(struct gk20a *g, bool enable)
{
g->gr->sw_ready = enable;
}
void nvgpu_gr_override_ecc_val(struct gk20a *g, u32 ecc_val)
{
g->gr->fecs_feature_override_ecc_val = ecc_val;
}

View File

@@ -25,6 +25,8 @@
#include <nvgpu/types.h> #include <nvgpu/types.h>
struct gk20a;
int nvgpu_gr_prepare_sw(struct gk20a *g); int nvgpu_gr_prepare_sw(struct gk20a *g);
int nvgpu_gr_enable_hw(struct gk20a *g); int nvgpu_gr_enable_hw(struct gk20a *g);
int nvgpu_gr_reset(struct gk20a *g); int nvgpu_gr_reset(struct gk20a *g);
@@ -40,5 +42,7 @@ void nvgpu_gr_free(struct gk20a *g);
int nvgpu_gr_disable_ctxsw(struct gk20a *g); int nvgpu_gr_disable_ctxsw(struct gk20a *g);
int nvgpu_gr_enable_ctxsw(struct gk20a *g); int nvgpu_gr_enable_ctxsw(struct gk20a *g);
int nvgpu_gr_halt_pipe(struct gk20a *g); int nvgpu_gr_halt_pipe(struct gk20a *g);
void nvgpu_gr_remove_support(struct gk20a *g);
void nvgpu_gr_sw_ready(struct gk20a *g, bool enable);
void nvgpu_gr_override_ecc_val(struct gk20a *g, u32 ecc_val);
#endif /* NVGPU_GR_H */ #endif /* NVGPU_GR_H */

View File

@@ -52,7 +52,6 @@
#include <nvgpu/pmu/pmu_pstate.h> #include <nvgpu/pmu/pmu_pstate.h>
#include <nvgpu/cyclestats_snapshot.h> #include <nvgpu/cyclestats_snapshot.h>
#include "common/gr/gr_priv.h"
#include "platform_gk20a.h" #include "platform_gk20a.h"
#include "sysfs.h" #include "sysfs.h"
#include "vgpu/vgpu_linux.h" #include "vgpu/vgpu_linux.h"
@@ -760,8 +759,7 @@ void gk20a_remove_support(struct gk20a *g)
g->sec2.remove_support(&g->sec2); g->sec2.remove_support(&g->sec2);
} }
if (g->gr->remove_support) nvgpu_gr_remove_support(g);
g->gr->remove_support(g);
if (g->mm.remove_ce_support) if (g->mm.remove_ce_support)
g->mm.remove_ce_support(&g->mm); g->mm.remove_ce_support(&g->mm);
@@ -1236,7 +1234,7 @@ void gk20a_driver_start_unload(struct gk20a *g)
nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true); nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true);
/* GR SW ready needs to be invalidated at this time with the busy lock /* GR SW ready needs to be invalidated at this time with the busy lock
* held to prevent a racing condition on the gr/mm code */ * held to prevent a racing condition on the gr/mm code */
g->gr->sw_ready = false; nvgpu_gr_sw_ready(g, false);
g->sw_ready = false; g->sw_ready = false;
up_write(&l->busy_lock); up_write(&l->busy_lock);
@@ -1286,7 +1284,7 @@ static int nvgpu_read_fuse_overrides(struct gk20a *g)
g->tpc_fs_mask_user = ~value; g->tpc_fs_mask_user = ~value;
break; break;
case GP10B_FUSE_OPT_ECC_EN: case GP10B_FUSE_OPT_ECC_EN:
g->gr->fecs_feature_override_ecc_val = value; nvgpu_gr_override_ecc_val(g, value);
break; break;
default: default:
nvgpu_err(g, "ignore unknown fuse override %08x", fuse); nvgpu_err(g, "ignore unknown fuse override %08x", fuse);

View File

@@ -26,6 +26,7 @@
#include <nvgpu/gr/config.h> #include <nvgpu/gr/config.h>
#include <nvgpu/gr/obj_ctx.h> #include <nvgpu/gr/obj_ctx.h>
#include <nvgpu/gr/gr_falcon.h> #include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/power_features/cg.h> #include <nvgpu/power_features/cg.h>
#include <nvgpu/power_features/pg.h> #include <nvgpu/power_features/pg.h>
#include <nvgpu/pmu/pmu_perfmon.h> #include <nvgpu/pmu/pmu_perfmon.h>
@@ -898,7 +899,7 @@ static ssize_t tpc_fs_mask_store(struct device *dev,
nvgpu_gr_config_deinit(g, g->gr->config); nvgpu_gr_config_deinit(g, g->gr->config);
/* Cause next poweron to reinit just gr */ /* Cause next poweron to reinit just gr */
g->gr->sw_ready = false; nvgpu_gr_sw_ready(g, false);
} }
return count; return count;