From 7e5b8b2ccea0420ac5bdc60c333f3b3050f5c235 Mon Sep 17 00:00:00 2001 From: rmylavarapu Date: Thu, 23 Jan 2020 11:23:06 +0530 Subject: [PATCH] gpu: nvgpu: Refactor PERF unit -Created perf.h file and moved all private functions and structures into it -Created single sw_setup/pmu_setup for whole perf unit -Changed public function and structure names as per standard format -Deleted lpwr unit specific file from make file as it is no longer used -Removed support_vfe and support_changeseq flags as it is no longer used -Removed clk_set_boot_fll_clks_per_clk_domain function as it is no longer used for tu10a -Removed perf unit headers from pmuif folder NVGPU-4448 Change-Id: Ia29e5b5a1a960b5474a929d8797542bf6c0eccf1 Signed-off-by: rmylavarapu Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2283587 Tested-by: mobile promotions Reviewed-by: mobile promotions --- arch/nvgpu-common.yaml | 5 +- drivers/gpu/nvgpu/Makefile | 4 +- drivers/gpu/nvgpu/Makefile.sources | 4 +- drivers/gpu/nvgpu/common/clk_arb/clk_arb.c | 4 +- .../gpu/nvgpu/common/clk_arb/clk_arb_gv100.c | 4 +- drivers/gpu/nvgpu/common/pmu/clk/clk.c | 7 +- drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c | 97 +-------------- .../gpu/nvgpu/common/pmu/perf/change_seq.c | 21 ++-- .../gpu/nvgpu/common/pmu/perf/change_seq.h | 5 +- .../common/pmu/perf/{perf_ps35.c => perf.c} | 114 ++++++++++++++++-- .../common/pmu/perf/{pmu_perf.c => perf.h} | 63 +++++----- drivers/gpu/nvgpu/common/pmu/perf/pstate.c | 35 ++---- drivers/gpu/nvgpu/common/pmu/perf/pstate.h | 5 +- drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c | 22 ++-- drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.h | 5 +- drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c | 24 ++-- drivers/gpu/nvgpu/common/pmu/perf/vfe_var.h | 5 +- drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gp106.c | 19 +-- drivers/gpu/nvgpu/common/pmu/pmu_pstate.c | 100 ++------------- .../pmu/super_surface/super_surface_priv.h | 3 +- drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c | 14 +-- .../gpu/nvgpu/common/pmu/volt/volt_policy.c | 8 +- drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c | 32 ++--- drivers/gpu/nvgpu/hal/clk/clk_tu104.c | 2 +- drivers/gpu/nvgpu/hal/init/hal_tu104.c | 6 +- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 4 - drivers/gpu/nvgpu/include/nvgpu/pmu.h | 3 +- drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h | 4 +- drivers/gpu/nvgpu/include/nvgpu/pmu/cmd.h | 3 +- drivers/gpu/nvgpu/include/nvgpu/pmu/msg.h | 3 +- drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h | 60 +++++---- .../gpu/nvgpu/include/nvgpu/pmu/pmuif/perf.h | 81 ------------- drivers/gpu/nvgpu/os/linux/debug_s_param.c | 4 +- 33 files changed, 297 insertions(+), 473 deletions(-) rename drivers/gpu/nvgpu/common/pmu/perf/{perf_ps35.c => perf.c} (61%) rename drivers/gpu/nvgpu/common/pmu/perf/{pmu_perf.c => perf.h} (52%) delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/perf.h diff --git a/arch/nvgpu-common.yaml b/arch/nvgpu-common.yaml index 22e58ba93..1277d11d5 100644 --- a/arch/nvgpu-common.yaml +++ b/arch/nvgpu-common.yaml @@ -652,7 +652,6 @@ pmu: include/nvgpu/pmu/pmuif/bios.h, include/nvgpu/pmu/pmuif/boardobj.h, include/nvgpu/pmu/pmuif/clk.h, - include/nvgpu/pmu/pmuif/perf.h, include/nvgpu/pmu/pmuif/pmgr.h, include/nvgpu/pmu/pmuif/seq.h, include/nvgpu/pmu/pmuif/thermsensor.h, @@ -731,13 +730,13 @@ pmu: sources: [ common/pmu/perf/change_seq.c, common/pmu/perf/change_seq.h, common/pmu/perf/ucode_perf_change_seq_inf.h, - common/pmu/perf/pmu_perf.c, common/pmu/perf/vfe_equ.c, common/pmu/perf/vfe_equ.h, common/pmu/perf/vfe_var.c, common/pmu/perf/vfe_var.h, common/pmu/perf/ucode_perf_vfe_inf.h, - common/pmu/perf/perf_ps35.c, + common/pmu/perf/perf.c, + common/pmu/perf/perf.h, common/pmu/perf/pstate.c, common/pmu/perf/pstate.h, common/pmu/perf/ucode_perf_pstate_inf.h, diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 8fe6ab12c..754d217f3 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -147,8 +147,7 @@ nvgpu-y += \ common/pmu/lsfm/lsfm_sw_tu104.o \ common/pmu/perf/vfe_var.o \ common/pmu/perf/vfe_equ.o \ - common/pmu/perf/pmu_perf.o \ - common/pmu/perf/perf_ps35.o \ + common/pmu/perf/perf.o \ common/pmu/perf/change_seq.o \ common/pmu/perf/pstate.o \ common/pmu/pmgr/pwrdev.o \ @@ -165,7 +164,6 @@ nvgpu-y += \ common/pmu/therm/thrmchannel.o \ common/pmu/therm/thrmpmu.o \ common/pmu/lpwr/rppg.o \ - common/pmu/lpwr/lpwr.o \ common/pmu/pmu_pstate.o \ common/pmu/pmu_rtos_init.o \ common/pmu/clk/clk_vin.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index bd7f986e6..482a3b112 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -446,17 +446,15 @@ srcs += \ common/pmu/ipc/pmu_msg.c \ common/pmu/ipc/pmu_queue.c \ common/pmu/ipc/pmu_seq.c \ - common/pmu/lpwr/lpwr.c \ common/pmu/lpwr/rppg.c \ common/pmu/lsfm/lsfm.c \ common/pmu/lsfm/lsfm_sw_gm20b.c \ common/pmu/lsfm/lsfm_sw_gp10b.c \ common/pmu/lsfm/lsfm_sw_gv100.c \ common/pmu/lsfm/lsfm_sw_tu104.c \ - common/pmu/perf/pmu_perf.c \ common/pmu/perf/vfe_equ.c \ common/pmu/perf/vfe_var.c \ - common/pmu/perf/perf_ps35.c \ + common/pmu/perf/perf.c \ common/pmu/perf/pstate.c \ common/pmu/perf/change_seq.c \ common/pmu/perfmon/pmu_perfmon.c \ diff --git a/drivers/gpu/nvgpu/common/clk_arb/clk_arb.c b/drivers/gpu/nvgpu/common/clk_arb/clk_arb.c index 4d5eecdff..ec721527b 100644 --- a/drivers/gpu/nvgpu/common/clk_arb/clk_arb.c +++ b/drivers/gpu/nvgpu/common/clk_arb/clk_arb.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -168,7 +168,7 @@ int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) /* GPC2CLK needs to be checked in two passes. The first determines the * relationships between GPC2CLK, SYS2CLK and XBAR2CLK, while the * second verifies that the clocks minimum is satisfied and sets - * the voltages,the later part is done in nvgpu_clk_set_req_fll_clk_ps35 + * the voltages,the later part is done in nvgpu_pmu_perf_changeseq_set_clks */ j = 0; num_points = 0; clk_cur = 0; for (i = 0; i < table->gpc2clk_num_points; i++) { diff --git a/drivers/gpu/nvgpu/common/clk_arb/clk_arb_gv100.c b/drivers/gpu/nvgpu/common/clk_arb/clk_arb_gv100.c index 7e86c5651..5dc49a984 100644 --- a/drivers/gpu/nvgpu/common/clk_arb/clk_arb_gv100.c +++ b/drivers/gpu/nvgpu/common/clk_arb/clk_arb_gv100.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -426,7 +426,7 @@ void gv100_clk_arb_run_arbiter_cb(struct nvgpu_clk_arb *arb) goto exit_arb; } - status = nvgpu_clk_set_req_fll_clk_ps35(g, &vf_point); + status = nvgpu_pmu_perf_changeseq_set_clks(g, &vf_point); if (status != 0) { nvgpu_err(g, "Unable to program frequency"); goto exit_arb; diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk.c b/drivers/gpu/nvgpu/common/pmu/clk/clk.c index 72095cc59..848594381 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -66,11 +66,6 @@ int nvgpu_clk_get_fll_clks(struct gk20a *g, { return g->pmu->clk_pmu->get_fll(g, setfllclk); } - -int nvgpu_clk_set_boot_fll_clk_tu10x(struct gk20a *g) -{ - return g->pmu->clk_pmu->set_boot_fll(g); -} #endif int nvgpu_clk_init_pmupstate(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c index 669c87605..cdc80f08f 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -1471,99 +1471,6 @@ done: return status; } -static int clk_set_boot_fll_clks_per_clk_domain(struct gk20a *g) -{ - struct nvgpu_pmu *pmu = g->pmu; - struct nv_pmu_rpc_perf_change_seq_queue_change rpc; - struct ctrl_perf_change_seq_change_input change_input; - struct clk_set_info *p0_clk_set_info; - struct nvgpu_clk_domain *pclk_domain; - int status = 0; - u8 i = 0, gpcclk_domain = 0; - u32 gpcclk_clkmhz = 0, gpcclk_voltuv = 0; - u32 vmin_uv = 0U, vmax_uv = 0U; - - (void) memset(&change_input, 0, - sizeof(struct ctrl_perf_change_seq_change_input)); - - BOARDOBJGRP_FOR_EACH(&(g->pmu->clk_pmu->clk_domainobjs->super.super), - struct nvgpu_clk_domain *, pclk_domain, i) { - - p0_clk_set_info = nvgpu_pmu_perf_pstate_get_clk_set_info(g, - CTRL_PERF_PSTATE_P0, pclk_domain->domain); - - switch (pclk_domain->api_domain) { - case CTRL_CLK_DOMAIN_GPCCLK: - gpcclk_domain = i; - gpcclk_clkmhz = p0_clk_set_info->max_mhz; - change_input.clk[i].clk_freq_khz = - (u32)p0_clk_set_info->max_mhz * 1000U; - change_input.clk_domains_mask.super.data[0] |= - (u32) BIT(i); - break; - case CTRL_CLK_DOMAIN_XBARCLK: - case CTRL_CLK_DOMAIN_SYSCLK: - case CTRL_CLK_DOMAIN_NVDCLK: - case CTRL_CLK_DOMAIN_HOSTCLK: - change_input.clk[i].clk_freq_khz = - (u32)p0_clk_set_info->max_mhz * 1000U; - change_input.clk_domains_mask.super.data[0] |= - (u32) BIT(i); - break; - default: - nvgpu_pmu_dbg(g, "Fixed clock domain"); - break; - } - } - - change_input.pstate_index = - nvgpu_get_pstate_entry_idx(g, CTRL_PERF_PSTATE_P0); - change_input.flags = (u32)CTRL_PERF_CHANGE_SEQ_CHANGE_FORCE; - change_input.vf_points_cache_counter = 0xFFFFFFFFU; - - status = nvgpu_clk_domain_freq_to_volt(g, gpcclk_domain, - &gpcclk_clkmhz, &gpcclk_voltuv, CTRL_VOLT_DOMAIN_LOGIC); - - status = nvgpu_volt_get_vmin_vmax_ps35(g, &vmin_uv, &vmax_uv); - if (status != 0) { - nvgpu_pmu_dbg(g, "Get vmin,vmax failed, proceeding with " - "freq_to_volt value"); - } - if ((status == 0) && (vmin_uv > gpcclk_voltuv)) { - gpcclk_voltuv = vmin_uv; - nvgpu_pmu_dbg(g, "Vmin is higher than evaluated Volt"); - } - - if (gpcclk_voltuv > vmax_uv) { - nvgpu_err(g, "Error: Requested voltage is more than chip max"); - return -EINVAL; - } - - change_input.volt[0].voltage_uv = gpcclk_voltuv; - change_input.volt[0].voltage_min_noise_unaware_uv = gpcclk_voltuv; - change_input.volt_rails_mask.super.data[0] = 1U; - - /* RPC to PMU to queue to execute change sequence request*/ - (void) memset(&rpc, 0, sizeof( - struct nv_pmu_rpc_perf_change_seq_queue_change)); - rpc.change = change_input; - rpc.change.pstate_index = - nvgpu_get_pstate_entry_idx(g, CTRL_PERF_PSTATE_P0); - PMU_RPC_EXECUTE_CPB(status, pmu, PERF, - CHANGE_SEQ_QUEUE_CHANGE, &rpc, 0); - if (status != 0) { - nvgpu_err(g, "Failed to execute Change Seq RPC status=0x%x", - status); - } - - /* Wait for sync change to complete. */ - if ((rpc.change.flags & CTRL_PERF_CHANGE_SEQ_CHANGE_ASYNC) == 0U) { - nvgpu_msleep(20); - } - - return status; -} - static void clk_set_p0_clk_per_domain(struct gk20a *g, u8 *gpcclk_domain, u32 *gpcclk_clkmhz, struct nvgpu_clk_slave_freq *vf_point, @@ -1729,8 +1636,6 @@ int nvgpu_clk_domain_init_pmupstate(struct gk20a *g) #ifdef CONFIG_NVGPU_CLK_ARB g->pmu->clk_pmu->get_fll = clk_get_fll_clks_per_clk_domain; - g->pmu->clk_pmu->set_boot_fll = - clk_set_boot_fll_clks_per_clk_domain; g->pmu->clk_pmu->set_p0_clks = clk_set_p0_clk_per_domain; #endif diff --git a/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c b/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c index 99bf6f253..757914172 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -36,6 +36,7 @@ #include #include "change_seq.h" +#include "perf.h" static int perf_change_seq_sw_setup_super(struct gk20a *g, struct change_seq *p_change_seq) @@ -71,10 +72,10 @@ perf_change_seq_sw_setup_super_exit: return status; } -int nvgpu_perf_change_seq_sw_setup(struct gk20a *g) +int perf_change_seq_sw_setup(struct gk20a *g) { struct change_seq_pmu *perf_change_seq_pmu = - &(g->perf_pmu->changeseq_pmu); + &(g->pmu->perf_pmu->changeseq_pmu); int status = 0; nvgpu_log_fn(g, " "); @@ -105,7 +106,7 @@ static void build_change_seq_boot (struct gk20a *g) { struct nvgpu_pmu *pmu = g->pmu; struct change_seq_pmu *perf_change_seq_pmu = - &(g->perf_pmu->changeseq_pmu); + &(g->pmu->perf_pmu->changeseq_pmu); struct nvgpu_clk_domain *pdomain; struct clk_set_info *p0_info; struct change_seq_pmu_script *script_last = @@ -167,13 +168,13 @@ static void build_change_seq_boot (struct gk20a *g) return; } -int nvgpu_perf_change_seq_pmu_setup(struct gk20a *g) +int perf_change_seq_pmu_setup(struct gk20a *g) { struct nv_pmu_rpc_perf_change_seq_info_get info_get; struct nv_pmu_rpc_perf_change_seq_info_set info_set; struct nvgpu_pmu *pmu = g->pmu; struct change_seq_pmu *perf_change_seq_pmu = - &(g->perf_pmu->changeseq_pmu); + &(g->pmu->perf_pmu->changeseq_pmu); int status; /* Do this till we enable performance table */ @@ -256,13 +257,13 @@ perf_change_seq_pmu_setup_exit: return status; } -int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, +int nvgpu_pmu_perf_changeseq_set_clks(struct gk20a *g, struct nvgpu_clk_slave_freq *vf_point) { struct nvgpu_pmu *pmu = g->pmu; struct nv_pmu_rpc_perf_change_seq_queue_change rpc; struct ctrl_perf_change_seq_change_input change_input; - struct change_seq_pmu *change_seq_pmu = &g->perf_pmu->changeseq_pmu; + struct change_seq_pmu *change_seq_pmu = &g->pmu->perf_pmu->changeseq_pmu; int status = 0; u8 gpcclk_domain = 0U; u32 gpcclk_voltuv = 0U, gpcclk_clkmhz = 0U; @@ -280,7 +281,7 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, change_input.flags = (u32)CTRL_PERF_CHANGE_SEQ_CHANGE_FORCE; change_input.vf_points_cache_counter = 0xFFFFFFFFU; - status = nvgpu_vfe_get_freq_margin_limit(g, &fmargin_mhz); + status = nvgpu_pmu_perf_vfe_get_freq_margin(g, &fmargin_mhz); if (status != 0) { nvgpu_err(g, "Failed to fetch Fmargin status=0x%x", status); return status; @@ -290,7 +291,7 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, status = nvgpu_clk_domain_freq_to_volt(g, gpcclk_domain, &gpcclk_clkmhz, &gpcclk_voltuv, CTRL_VOLT_DOMAIN_LOGIC); - status = nvgpu_vfe_get_volt_margin_limit(g, &vmargin_uv); + status = nvgpu_pmu_perf_vfe_get_volt_margin(g, &vmargin_uv); if (status != 0) { nvgpu_err(g, "Failed to fetch Vmargin status=0x%x", status); return status; diff --git a/drivers/gpu/nvgpu/common/pmu/perf/change_seq.h b/drivers/gpu/nvgpu/common/pmu/perf/change_seq.h index 0c3883518..75dbfc337 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/change_seq.h +++ b/drivers/gpu/nvgpu/common/pmu/perf/change_seq.h @@ -1,7 +1,7 @@ /* * general clock structures & definitions * - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,4 +29,7 @@ #define SEQ_SCRIPT_LAST 0x1U #define SEQ_SCRIPT_QUERY 0x2U +int perf_change_seq_sw_setup(struct gk20a *g); +int perf_change_seq_pmu_setup(struct gk20a *g); + #endif /* NVGPU_CHANGE_SEQ_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/perf/perf_ps35.c b/drivers/gpu/nvgpu/common/pmu/perf/perf.c similarity index 61% rename from drivers/gpu/nvgpu/common/pmu/perf/perf_ps35.c rename to drivers/gpu/nvgpu/common/pmu/perf/perf.c index 6daf9f529..515b23a4d 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/perf_ps35.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/perf.c @@ -1,7 +1,6 @@ /* - * GV100 PERF * - * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,10 +28,19 @@ #include #include +#include "ucode_perf_change_seq_inf.h" +#include "ucode_perf_pstate_inf.h" +#include "ucode_perf_vfe_inf.h" +#include "vfe_equ.h" +#include "vfe_var.h" +#include "change_seq.h" +#include "pstate.h" +#include "perf.h" + static int pmu_set_boot_clk_runcb_fn(void *arg) { struct gk20a *g = (struct gk20a *)arg; - struct perf_pmupstate *perf_pmu = g->perf_pmu; + struct perf_pmupstate *perf_pmu = g->pmu->perf_pmu; struct nvgpu_vfe_invalidate *vfe_init = &perf_pmu->vfe_init; nvgpu_log_fn(g, "thread start"); @@ -56,8 +64,8 @@ static int tu104_pmu_handle_perf_event(struct gk20a *g, void *pmumsg) { struct pmu_nvgpu_rpc_perf_event *msg = (struct pmu_nvgpu_rpc_perf_event *)pmumsg; - struct perf_pmupstate *perf_pmu = g->perf_pmu; - struct change_seq_pmu *change_pmu = &g->perf_pmu->changeseq_pmu; + struct perf_pmupstate *perf_pmu = g->pmu->perf_pmu; + struct change_seq_pmu *change_pmu = &g->pmu->perf_pmu->changeseq_pmu; nvgpu_log_fn(g, " "); switch (msg->rpc_hdr.function) { @@ -81,7 +89,7 @@ static int tu104_pmu_handle_perf_event(struct gk20a *g, void *pmumsg) static int perf_pmu_init_vfe_perf_event(struct gk20a *g) { - struct perf_pmupstate *perf_pmu = g->perf_pmu; + struct perf_pmupstate *perf_pmu = g->pmu->perf_pmu; char thread_name[64]; int err = 0; @@ -102,7 +110,7 @@ static int perf_pmu_init_vfe_perf_event(struct gk20a *g) } -int nvgpu_perf_pmu_vfe_load_ps35(struct gk20a *g) +int nvgpu_pmu_perf_load(struct gk20a *g) { struct nvgpu_pmu *pmu = g->pmu; struct nv_pmu_rpc_struct_perf_load rpc; @@ -122,8 +130,98 @@ int nvgpu_perf_pmu_vfe_load_ps35(struct gk20a *g) if (status != 0) { nvgpu_err(g, "Failed to execute RPC status=0x%x", status); - nvgpu_thread_stop(&g->perf_pmu->vfe_init.state_task); + nvgpu_thread_stop(&g->pmu->perf_pmu->vfe_init.state_task); } return status; } + +int nvgpu_pmu_perf_init(struct gk20a *g) +{ + /* If already allocated, do not re-allocate */ + if (g->pmu->perf_pmu != NULL) { + return 0; + } + + g->pmu->perf_pmu = nvgpu_kzalloc(g, sizeof(*g->pmu->perf_pmu)); + if (g->pmu->perf_pmu == NULL) { + return -ENOMEM; + } + + return 0; +} + +static void vfe_thread_stop_cb(void *data) +{ + struct nvgpu_cond *cond = (struct nvgpu_cond *)data; + + nvgpu_cond_signal(cond); +} + +void nvgpu_pmu_perf_deinit(struct gk20a *g) +{ + if (nvgpu_thread_is_running(&g->pmu->perf_pmu->vfe_init.state_task)) { + nvgpu_thread_stop_graceful(&g->pmu->perf_pmu->vfe_init.state_task, + vfe_thread_stop_cb, &g->pmu->perf_pmu->vfe_init.wq); + } + nvgpu_cond_destroy(&g->pmu->perf_pmu->vfe_init.wq); + nvgpu_kfree(g, g->pmu->perf_pmu); + g->pmu->perf_pmu = NULL; +} + +int nvgpu_pmu_perf_sw_setup(struct gk20a *g) +{ + int err; + nvgpu_log_fn(g, " "); + + err = perf_vfe_var_sw_setup(g); + if (err != 0) { + return err; + } + + err = perf_vfe_equ_sw_setup(g); + if (err != 0) { + return err; + } + + err = perf_pstate_sw_setup(g); + if (err != 0) { + return err; + } + + err = perf_change_seq_sw_setup(g); + if (err != 0) { + return err; + } + + return 0; +} + +int nvgpu_pmu_perf_pmu_setup(struct gk20a *g) +{ + int err; + nvgpu_log_fn(g, " "); + + err = perf_vfe_var_pmu_setup(g); + if (err != 0) { + return err; + } + + err = perf_vfe_equ_pmu_setup(g); + if (err != 0) { + return err; + } + + err = perf_pstate_pmu_setup(g); + if (err != 0) { + return err; + } + + err = perf_change_seq_pmu_setup(g); + if (err != 0) { + return err; + } + + return 0; +} + diff --git a/drivers/gpu/nvgpu/common/pmu/perf/pmu_perf.c b/drivers/gpu/nvgpu/common/pmu/perf/perf.h similarity index 52% rename from drivers/gpu/nvgpu/common/pmu/perf/pmu_perf.c rename to drivers/gpu/nvgpu/common/pmu/perf/perf.h index 3480f7648..787144e06 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/pmu_perf.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/perf.h @@ -1,5 +1,7 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * general perf structures & definitions + * + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,41 +22,36 @@ * DEALINGS IN THE SOFTWARE. */ -#include -#include -#include -#include -#include +#ifndef PMU_PERF_H_ +#define PMU_PERF_H_ -int nvgpu_perf_pmu_init_pmupstate(struct gk20a *g) -{ - /* If already allocated, do not re-allocate */ - if (g->perf_pmu != NULL) { - return 0; - } +/* PERF RPC ID Definitions */ +#define NV_PMU_RPC_ID_PERF_VFE_CALLBACK 0x01U +#define NV_PMU_RPC_ID_PERF_SEQ_COMPLETION 0x02U +#define NV_PMU_RPC_ID_PERF_PSTATES_INVALIDATE 0x03U - g->perf_pmu = nvgpu_kzalloc(g, sizeof(*g->perf_pmu)); - if (g->perf_pmu == NULL) { - return -ENOMEM; - } +/* + * Defines the structure that holds data + * used to execute LOAD RPC. + */ +struct nv_pmu_rpc_struct_perf_load { + /* [IN/OUT] Must be first field in RPC structure */ + struct nv_pmu_rpc_header hdr; + bool b_load; + u32 scratch[1]; +}; - return 0; -} +/* + * Simply a union of all specific PERF messages. Forms the general packet + * exchanged between the Kernel and PMU when sending and receiving PERF messages + * (respectively). + */ -static void vfe_thread_stop_cb(void *data) -{ - struct nvgpu_cond *cond = (struct nvgpu_cond *)data; +struct pmu_nvgpu_rpc_perf_event { + struct pmu_hdr msg_hdr; + struct pmu_nvgpu_rpc_header rpc_hdr; +}; - nvgpu_cond_signal(cond); -} +int nvgpu_get_pstate_entry_idx(struct gk20a *g, u32 num); -void nvgpu_perf_pmu_free_pmupstate(struct gk20a *g) -{ - if (nvgpu_thread_is_running(&g->perf_pmu->vfe_init.state_task)) { - nvgpu_thread_stop_graceful(&g->perf_pmu->vfe_init.state_task, - vfe_thread_stop_cb, &g->perf_pmu->vfe_init.wq); - } - nvgpu_cond_destroy(&g->perf_pmu->vfe_init.wq); - nvgpu_kfree(g, g->perf_pmu); - g->perf_pmu = NULL; -} +#endif /* PMU_PERF_H_ */ diff --git a/drivers/gpu/nvgpu/common/pmu/perf/pstate.c b/drivers/gpu/nvgpu/common/pmu/perf/pstate.c index ad1db28e2..dbaeebdb1 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/pstate.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/pstate.c @@ -1,7 +1,7 @@ /* * general p state infrastructure * - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -35,10 +35,11 @@ #include "ucode_perf_pstate_inf.h" #include "pstate.h" +#include "perf.h" int nvgpu_get_pstate_entry_idx(struct gk20a *g, u32 num) { - struct pstates *pstates = &(g->perf_pmu->pstatesobjs); + struct pstates *pstates = &(g->pmu->perf_pmu->pstatesobjs); struct pstate *pstate; u8 i; @@ -169,7 +170,7 @@ static struct pstate *pstate_construct(struct gk20a *g, void *args) static int pstate_insert(struct gk20a *g, struct pstate *pstate, u8 index) { - struct pstates *pstates = &(g->perf_pmu->pstatesobjs); + struct pstates *pstates = &(g->pmu->perf_pmu->pstatesobjs); int err; err = boardobjgrp_objinsert(&pstates->super.super, @@ -359,13 +360,13 @@ static int perf_pstate_pmudata_instget(struct gk20a *g, return 0; } -int nvgpu_pmu_perf_pstate_sw_setup(struct gk20a *g) +int perf_pstate_sw_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; status = nvgpu_boardobjgrp_construct_e32(g, - &g->perf_pmu->pstatesobjs.super); + &g->pmu->perf_pmu->pstatesobjs.super); if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for pstate, status - 0x%x", @@ -373,7 +374,7 @@ int nvgpu_pmu_perf_pstate_sw_setup(struct gk20a *g) goto done; } - pboardobjgrp = &g->perf_pmu->pstatesobjs.super.super; + pboardobjgrp = &g->pmu->perf_pmu->pstatesobjs.super.super; BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, PERF, PSTATE); @@ -386,7 +387,7 @@ int nvgpu_pmu_perf_pstate_sw_setup(struct gk20a *g) goto done; } - g->perf_pmu->pstatesobjs.num_clk_domains = + g->pmu->perf_pmu->pstatesobjs.num_clk_domains = VBIOS_PSTATE_CLOCK_ENTRY_6X_COUNT; pboardobjgrp->pmudatainit = perf_pstate_pmudatainit; @@ -402,12 +403,12 @@ done: return status; } -int nvgpu_pmu_perf_pstate_pmu_setup(struct gk20a *g) +int perf_pstate_pmu_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; - pboardobjgrp = &g->perf_pmu->pstatesobjs.super.super; + pboardobjgrp = &g->pmu->perf_pmu->pstatesobjs.super.super; if (!pboardobjgrp->bconstructed) { return -EINVAL; } @@ -420,7 +421,7 @@ int nvgpu_pmu_perf_pstate_pmu_setup(struct gk20a *g) static struct pstate *perf_pstate_find(struct gk20a *g, u32 num) { - struct pstates *pstates = &(g->perf_pmu->pstatesobjs); + struct pstates *pstates = &(g->pmu->perf_pmu->pstatesobjs); struct pstate *pstate; u8 i; @@ -452,17 +453,3 @@ struct clk_set_info *nvgpu_pmu_perf_pstate_get_clk_set_info(struct gk20a *g, } return NULL; } - -int nvgpu_perf_pstate_get_lpwr_index(struct gk20a *g, u32 num, u8 *lpwr_idx) -{ - struct pstate *pstate = perf_pstate_find(g, num); - - if (pstate == NULL) { - return -EINVAL; - } - - *lpwr_idx = pstate->lpwr_entry_idx; - return 0; -} - - diff --git a/drivers/gpu/nvgpu/common/pmu/perf/pstate.h b/drivers/gpu/nvgpu/common/pmu/perf/pstate.h index cf34d7d0c..996cd4d7f 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/pstate.h +++ b/drivers/gpu/nvgpu/common/pmu/perf/pstate.h @@ -1,7 +1,7 @@ /* * general p state infrastructure * - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -42,4 +42,7 @@ struct pstate { struct clk_set_info_list clklist; }; +int perf_pstate_sw_setup(struct gk20a *g); +int perf_pstate_pmu_setup(struct gk20a *g); + #endif /* NVGPU_PERF_PSTATE_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c b/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c index c8e0fc168..49e25bc79 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -98,7 +98,7 @@ static int vfe_equ_build_depending_mask_super(struct gk20a *g, { struct vfe_var *tmp_vfe_var; struct boardobjgrp *pboardobjgrp = - &g->perf_pmu->vfe_varobjs.super.super; + &g->pmu->perf_pmu->vfe_varobjs.super.super; tmp_vfe_var = (struct vfe_var *)(void *)BOARDOBJGRP_OBJ_GET_BY_IDX( pboardobjgrp, pvfe_equ->var_idx); @@ -845,7 +845,7 @@ done: return status; } -int nvgpu_vfe_equ_sw_setup(struct gk20a *g) +int perf_vfe_equ_sw_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; @@ -853,7 +853,7 @@ int nvgpu_vfe_equ_sw_setup(struct gk20a *g) struct vfe_vars *pvfevarobjs; status = nvgpu_boardobjgrp_construct_e255(g, - &g->perf_pmu->vfe_equobjs.super); + &g->pmu->perf_pmu->vfe_equobjs.super); if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for clk domain, " @@ -861,9 +861,9 @@ int nvgpu_vfe_equ_sw_setup(struct gk20a *g) goto done; } - pboardobjgrp = &g->perf_pmu->vfe_equobjs.super.super; - pvfeequobjs = &(g->perf_pmu->vfe_equobjs); - pvfevarobjs = &(g->perf_pmu->vfe_varobjs); + pboardobjgrp = &g->pmu->perf_pmu->vfe_equobjs.super.super; + pvfeequobjs = &(g->pmu->perf_pmu->vfe_equobjs); + pvfevarobjs = &(g->pmu->perf_pmu->vfe_varobjs); BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, PERF, VFE_EQU); @@ -894,12 +894,12 @@ done: return status; } -int nvgpu_vfe_equ_pmu_setup(struct gk20a *g) +int perf_vfe_equ_pmu_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; - pboardobjgrp = &g->perf_pmu->vfe_equobjs.super.super; + pboardobjgrp = &g->pmu->perf_pmu->vfe_equobjs.super.super; if (!pboardobjgrp->bconstructed) { return -EINVAL; @@ -911,7 +911,7 @@ int nvgpu_vfe_equ_pmu_setup(struct gk20a *g) return status; } -int nvgpu_vfe_get_volt_margin_limit(struct gk20a *g, u32 *vmargin_uv) +int nvgpu_pmu_perf_vfe_get_volt_margin(struct gk20a *g, u32 *vmargin_uv) { struct nvgpu_pmu *pmu = g->pmu; struct nv_pmu_rpc_struct_perf_vfe_eval rpc; @@ -938,7 +938,7 @@ int nvgpu_vfe_get_volt_margin_limit(struct gk20a *g, u32 *vmargin_uv) return status; } -int nvgpu_vfe_get_freq_margin_limit(struct gk20a *g, u32 *fmargin_mhz) +int nvgpu_pmu_perf_vfe_get_freq_margin(struct gk20a *g, u32 *fmargin_mhz) { struct nvgpu_pmu *pmu = g->pmu; struct nv_pmu_rpc_struct_perf_vfe_eval rpc; diff --git a/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.h b/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.h index 16908ac3b..435603697 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.h +++ b/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.h @@ -1,7 +1,7 @@ /* * general perf structures & definitions * - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -63,4 +63,7 @@ struct vfe_equ_scalar { struct vfe_equ super; u8 equ_idx_to_scale; }; + +int perf_vfe_equ_sw_setup(struct gk20a *g); +int perf_vfe_equ_pmu_setup(struct gk20a *g); #endif /* NVGPU_PERF_VFE_EQU_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c b/drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c index 7f64d569d..030c0844d 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -1274,8 +1274,8 @@ static int vfe_var_boardobj_grp_get_status(struct gk20a *g) int status; u8 index; - pboardobjgrp = &g->perf_pmu->vfe_varobjs.super.super; - pboardobjgrpmask = &g->perf_pmu->vfe_varobjs.super.mask.super; + pboardobjgrp = &g->pmu->perf_pmu->vfe_varobjs.super.super; + pboardobjgrpmask = &g->pmu->perf_pmu->vfe_varobjs.super.mask.super; status = pboardobjgrp->pmugetstatus(g, pboardobjgrp, pboardobjgrpmask); if (status != 0) { @@ -1314,14 +1314,14 @@ static int vfe_var_boardobj_grp_get_status(struct gk20a *g) return 0; } -int nvgpu_vfe_var_sw_setup(struct gk20a *g) +int perf_vfe_var_sw_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; struct vfe_vars *pvfevarobjs; status = nvgpu_boardobjgrp_construct_e32(g, - &g->perf_pmu->vfe_varobjs.super); + &g->pmu->perf_pmu->vfe_varobjs.super); if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for clk domain, " @@ -1329,8 +1329,8 @@ int nvgpu_vfe_var_sw_setup(struct gk20a *g) goto done; } - pboardobjgrp = &g->perf_pmu->vfe_varobjs.super.super; - pvfevarobjs = &g->perf_pmu->vfe_varobjs; + pboardobjgrp = &g->pmu->perf_pmu->vfe_varobjs.super.super; + pvfevarobjs = &g->pmu->perf_pmu->vfe_varobjs; BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, PERF, VFE_VAR); @@ -1357,7 +1357,7 @@ int nvgpu_vfe_var_sw_setup(struct gk20a *g) } status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g, - &g->perf_pmu->vfe_varobjs.super.super, + &g->pmu->perf_pmu->vfe_varobjs.super.super, perf, PERF, vfe_var, VFE_VAR); if (status != 0) { nvgpu_err(g, @@ -1371,12 +1371,12 @@ done: return status; } -int nvgpu_vfe_var_pmu_setup(struct gk20a *g) +int perf_vfe_var_pmu_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; - pboardobjgrp = &g->perf_pmu->vfe_varobjs.super.super; + pboardobjgrp = &g->pmu->perf_pmu->vfe_varobjs.super.super; if (!pboardobjgrp->bconstructed) { return -EINVAL; @@ -1388,7 +1388,7 @@ int nvgpu_vfe_var_pmu_setup(struct gk20a *g) return status; } -int nvgpu_vfe_var_get_s_param(struct gk20a *g, u64 *s_param) +int nvgpu_pmu_perf_vfe_get_s_param(struct gk20a *g, u64 *s_param) { struct boardobjgrp *pboardobjgrp; struct boardobj *pboardobj = NULL; @@ -1402,7 +1402,7 @@ int nvgpu_vfe_var_get_s_param(struct gk20a *g, u64 *s_param) return status; } - pboardobjgrp = &g->perf_pmu->vfe_varobjs.super.super; + pboardobjgrp = &g->pmu->perf_pmu->vfe_varobjs.super.super; BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) { single_sensed_fuse = (struct vfe_var_single_sensed_fuse *) diff --git a/drivers/gpu/nvgpu/common/pmu/perf/vfe_var.h b/drivers/gpu/nvgpu/common/pmu/perf/vfe_var.h index 9e7e2e92c..2696cd668 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/vfe_var.h +++ b/drivers/gpu/nvgpu/common/pmu/perf/vfe_var.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -98,4 +98,7 @@ struct vfe_var_single_sensed_temp { int temp_default; }; +int perf_vfe_var_sw_setup(struct gk20a *g); +int perf_vfe_var_pmu_setup(struct gk20a *g); + #endif /* NVGPU_PERF_VFE_VAR_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gp106.c b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gp106.c index 4ef31353d..bfa3943ff 100644 --- a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gp106.c +++ b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gp106.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -144,20 +144,5 @@ u32 gp106_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id) bool gp106_pmu_is_lpwr_feature_supported(struct gk20a *g, u32 feature_id) { - bool is_feature_supported = false; - - switch (feature_id) { - case PMU_PG_LPWR_FEATURE_RPPG: - is_feature_supported = nvgpu_lpwr_is_rppg_supported(g, - nvgpu_clk_arb_get_current_pstate(g)); - break; - case PMU_PG_LPWR_FEATURE_MSCG: - is_feature_supported = nvgpu_lpwr_is_mscg_supported(g, - nvgpu_clk_arb_get_current_pstate(g)); - break; - default: - is_feature_supported = false; - } - - return is_feature_supported; + return false; } diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c b/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c index 691e8b349..f3277a409 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c @@ -46,8 +46,8 @@ void nvgpu_pmu_pstate_deinit(struct gk20a *g) pmgr_pmu_free_pmupstate(g); nvgpu_therm_pmu_free_pmupstate(g, g->pmu); - if (g->perf_pmu != NULL) { - nvgpu_perf_pmu_free_pmupstate(g); + if (g->pmu->perf_pmu != NULL) { + nvgpu_pmu_perf_deinit(g); } if (g->pmu->clk_pmu != NULL) { @@ -124,9 +124,9 @@ static int pmu_pstate_init(struct gk20a *g) return err; } - err = nvgpu_perf_pmu_init_pmupstate(g); + err = nvgpu_pmu_perf_init(g); if (err != 0) { - nvgpu_perf_pmu_free_pmupstate(g); + nvgpu_pmu_perf_deinit(g); return err; } @@ -162,8 +162,7 @@ static int pmu_pstate_clk_sw_setup(struct gk20a *g) return err; } - if (g->ops.clk.support_vf_point && - g->ops.pmu_perf.support_vfe) { + if (g->ops.clk.support_vf_point) { err = nvgpu_clk_vf_point_sw_setup(g); if (err != 0) { nvgpu_clk_vf_point_free_pmupstate(g); @@ -180,38 +179,6 @@ static int pmu_pstate_clk_sw_setup(struct gk20a *g) return 0; } -static int pmu_pstate_perf_sw_setup(struct gk20a *g) -{ - int err; - nvgpu_log_fn(g, " "); - - if (g->ops.pmu_perf.support_vfe) { - err = nvgpu_vfe_var_sw_setup(g); - if (err != 0) { - return err; - } - - err = nvgpu_vfe_equ_sw_setup(g); - if (err != 0) { - return err; - } - } - - err = nvgpu_pmu_perf_pstate_sw_setup(g); - if (err != 0) { - return err; - } - - if (g->ops.pmu_perf.support_changeseq) { - err = nvgpu_perf_change_seq_sw_setup(g); - if (err != 0) { - return err; - } - } - - return 0; -} - /*sw setup for pstate components*/ int nvgpu_pmu_pstate_sw_setup(struct gk20a *g) { @@ -247,7 +214,7 @@ int nvgpu_pmu_pstate_sw_setup(struct gk20a *g) return err; } - err = pmu_pstate_perf_sw_setup(g); + err = nvgpu_pmu_perf_sw_setup(g); if (err != 0) { nvgpu_err(g, "Perf sw setup failed"); goto err_perf_pmu_init_pmupstate; @@ -260,13 +227,6 @@ int nvgpu_pmu_pstate_sw_setup(struct gk20a *g) } } - if (g->ops.clk.support_lpwr_pg) { - err = nvgpu_lpwr_pg_setup(g); - if (err != 0) { - goto err_pmgr_pmu_init_pmupstate; - } - } - return 0; err_pmgr_pmu_init_pmupstate: @@ -274,7 +234,7 @@ err_pmgr_pmu_init_pmupstate: err_therm_pmu_init_pmupstate: nvgpu_therm_pmu_free_pmupstate(g, g->pmu); err_perf_pmu_init_pmupstate: - nvgpu_perf_pmu_free_pmupstate(g); + nvgpu_pmu_perf_deinit(g); return err; } @@ -304,8 +264,7 @@ static int pmu_pstate_clk_pmu_setup(struct gk20a *g) return err; } - if (g->ops.clk.support_vf_point && - g->ops.pmu_perf.support_vfe) { + if (g->ops.clk.support_vf_point) { err = nvgpu_clk_vf_point_pmu_setup(g); if (err != 0) { return err; @@ -325,38 +284,6 @@ static int pmu_pstate_clk_pmu_setup(struct gk20a *g) return 0; } -static int pmu_pstate_perf_pmu_setup(struct gk20a *g) -{ - int err; - nvgpu_log_fn(g, " "); - - if (g->ops.pmu_perf.support_vfe) { - err = nvgpu_vfe_var_pmu_setup(g); - if (err != 0) { - return err; - } - - err = nvgpu_vfe_equ_pmu_setup(g); - if (err != 0) { - return err; - } - } - - err = nvgpu_pmu_perf_pstate_pmu_setup(g); - if (err != 0) { - return err; - } - - if (g->ops.pmu_perf.support_changeseq) { - err = nvgpu_perf_change_seq_pmu_setup(g); - if (err != 0) { - return err; - } - } - - return 0; -} - /*sw setup for pstate components*/ int nvgpu_pmu_pstate_pmu_setup(struct gk20a *g) { @@ -388,7 +315,7 @@ int nvgpu_pmu_pstate_pmu_setup(struct gk20a *g) return err; } - err = pmu_pstate_perf_pmu_setup(g); + err = nvgpu_pmu_perf_pmu_setup(g); if (err != 0) { nvgpu_err(g, "Failed to send Perf pmu setup"); return err; @@ -398,12 +325,11 @@ int nvgpu_pmu_pstate_pmu_setup(struct gk20a *g) err = pmgr_domain_pmu_setup(g); } - if (g->ops.pmu_perf.support_vfe) { - err = g->ops.clk.perf_pmu_vfe_load(g); - if (err != 0) { - return err; - } + err = g->ops.clk.perf_pmu_vfe_load(g); + if (err != 0) { + return err; } + return err; } diff --git a/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h b/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h index b7416285e..33bcea587 100644 --- a/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h +++ b/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -27,7 +27,6 @@ #include #include #include -#include #include #include diff --git a/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c b/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c index 7f6bbbca4..cbf62e82d 100644 --- a/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c +++ b/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c @@ -446,7 +446,7 @@ static int volt_device_state_init(struct gk20a *g, /* Build VOLT_RAIL SW state from VOLT_DEVICE SW state. */ /* If VOLT_RAIL isn't supported, exit. */ - if (VOLT_RAIL_VOLT_3X_SUPPORTED(&g->perf_pmu->volt)) { + if (VOLT_RAIL_VOLT_3X_SUPPORTED(&g->pmu->perf_pmu->volt)) { rail_idx = nvgpu_volt_rail_volt_domain_convert_to_idx(g, pvolt_dev->volt_domain); if (rail_idx == CTRL_BOARDOBJ_IDX_INVALID) { @@ -456,7 +456,7 @@ static int volt_device_state_init(struct gk20a *g, goto done; } - pRail = VOLT_GET_VOLT_RAIL(&g->perf_pmu->volt, rail_idx); + pRail = VOLT_GET_VOLT_RAIL(&g->pmu->perf_pmu->volt, rail_idx); if (pRail == NULL) { nvgpu_err(g, "could not obtain ptr to rail object from rail index"); @@ -488,7 +488,7 @@ int volt_dev_pmu_setup(struct gk20a *g) nvgpu_log_info(g, " "); - pboardobjgrp = &g->perf_pmu->volt.volt_dev_metadata.volt_devices.super; + pboardobjgrp = &g->pmu->perf_pmu->volt.volt_dev_metadata.volt_devices.super; if (!pboardobjgrp->bconstructed) { return -EINVAL; @@ -510,7 +510,7 @@ int volt_dev_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); status = nvgpu_boardobjgrp_construct_e32(g, - &g->perf_pmu->volt.volt_dev_metadata.volt_devices); + &g->pmu->perf_pmu->volt.volt_dev_metadata.volt_devices); if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for volt rail, " @@ -518,12 +518,12 @@ int volt_dev_sw_setup(struct gk20a *g) goto done; } - pboardobjgrp = &g->perf_pmu->volt.volt_dev_metadata.volt_devices.super; + pboardobjgrp = &g->pmu->perf_pmu->volt.volt_dev_metadata.volt_devices.super; pboardobjgrp->pmudatainstget = _volt_device_devgrp_pmudata_instget; /* Obtain Voltage Rail Table from VBIOS */ - status = volt_get_volt_devices_table(g, &g->perf_pmu->volt. + status = volt_get_volt_devices_table(g, &g->pmu->perf_pmu->volt. volt_dev_metadata); if (status != 0) { goto done; @@ -542,7 +542,7 @@ int volt_dev_sw_setup(struct gk20a *g) } /* update calibration to fuse */ - BOARDOBJGRP_FOR_EACH(&(g->perf_pmu->volt.volt_dev_metadata.volt_devices. + BOARDOBJGRP_FOR_EACH(&(g->pmu->perf_pmu->volt.volt_dev_metadata.volt_devices. super), struct voltage_device *, pvolt_device, i) { status = volt_device_state_init(g, pvolt_device); diff --git a/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c b/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c index a5ca0d185..43dc3fa1f 100644 --- a/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c +++ b/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c @@ -357,7 +357,7 @@ int volt_policy_pmu_setup(struct gk20a *g) nvgpu_log_info(g, " "); pboardobjgrp = - &g->perf_pmu->volt.volt_policy_metadata.volt_policies.super; + &g->pmu->perf_pmu->volt.volt_policy_metadata.volt_policies.super; if (!pboardobjgrp->bconstructed) { return -EINVAL; @@ -377,7 +377,7 @@ int volt_policy_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); status = nvgpu_boardobjgrp_construct_e32(g, - &g->perf_pmu->volt.volt_policy_metadata.volt_policies); + &g->pmu->perf_pmu->volt.volt_policy_metadata.volt_policies); if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for volt rail, " @@ -386,13 +386,13 @@ int volt_policy_sw_setup(struct gk20a *g) } pboardobjgrp = - &g->perf_pmu->volt.volt_policy_metadata.volt_policies.super; + &g->pmu->perf_pmu->volt.volt_policy_metadata.volt_policies.super; pboardobjgrp->pmudatainstget = _volt_policy_devgrp_pmudata_instget; pboardobjgrp->pmudatainit = _volt_policy_grp_pmudatainit_super; /* Obtain Voltage Rail Table from VBIOS */ - status = volt_get_volt_policy_table(g, &g->perf_pmu->volt. + status = volt_get_volt_policy_table(g, &g->pmu->perf_pmu->volt. volt_policy_metadata); if (status != 0) { goto done; diff --git a/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c b/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c index 83ffb18cf..236fc0519 100644 --- a/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c +++ b/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c @@ -45,7 +45,7 @@ static int volt_rail_state_init(struct gk20a *g, for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { pvolt_rail->volt_delta_uv[i] = (int)NV_PMU_VOLT_VALUE_0V_IN_UV; - g->perf_pmu->volt.volt_rail_metadata.ext_rel_delta_uv[i] = + g->pmu->perf_pmu->volt.volt_rail_metadata.ext_rel_delta_uv[i] = NV_PMU_VOLT_VALUE_0V_IN_UV; } @@ -101,7 +101,7 @@ static int volt_rail_init_pmudata_super(struct gk20a *g, for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] + - (int)g->perf_pmu->volt.volt_rail_metadata.ext_rel_delta_uv[i]; + (int)g->pmu->perf_pmu->volt.volt_rail_metadata.ext_rel_delta_uv[i]; } status = nvgpu_boardobjgrpmask_export(&prail->volt_dev_mask.super, @@ -348,8 +348,8 @@ static int nvgpu_volt_rail_boardobj_grp_get_status(struct gk20a *g) nvgpu_log_info(g, " "); - pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super; - pboardobjgrpmask = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.mask.super; + pboardobjgrp = &g->pmu->perf_pmu->volt.volt_rail_metadata.volt_rails.super; + pboardobjgrpmask = &g->pmu->perf_pmu->volt.volt_rail_metadata.volt_rails.mask.super; status = pboardobjgrp->pmugetstatus(g, pboardobjgrp, pboardobjgrpmask); if (status != 0) { nvgpu_err(g, "err getting boardobjs from pmu"); @@ -385,7 +385,7 @@ int volt_rail_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); status = nvgpu_boardobjgrp_construct_e32(g, - &g->perf_pmu->volt.volt_rail_metadata.volt_rails); + &g->pmu->perf_pmu->volt.volt_rail_metadata.volt_rails); if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for volt rail, " @@ -393,16 +393,16 @@ int volt_rail_sw_setup(struct gk20a *g) goto done; } - pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super; + pboardobjgrp = &g->pmu->perf_pmu->volt.volt_rail_metadata.volt_rails.super; pboardobjgrp->pmudatainstget = _volt_rail_devgrp_pmudata_instget; pboardobjgrp->pmustatusinstget = _volt_rail_devgrp_pmustatus_instget; - g->perf_pmu->volt.volt_rail_metadata.pct_delta = + g->pmu->perf_pmu->volt.volt_rail_metadata.pct_delta = NV_PMU_VOLT_VALUE_0V_IN_UV; /* Obtain Voltage Rail Table from VBIOS */ - status = volt_get_volt_rail_table(g, &g->perf_pmu->volt. + status = volt_get_volt_rail_table(g, &g->pmu->perf_pmu->volt. volt_rail_metadata); if (status != 0) { goto done; @@ -421,7 +421,7 @@ int volt_rail_sw_setup(struct gk20a *g) } status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g, - &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super, + &g->pmu->perf_pmu->volt.volt_rail_metadata.volt_rails.super, volt, VOLT, volt_rail, VOLT_RAIL); if (status != 0) { nvgpu_err(g, @@ -431,7 +431,7 @@ int volt_rail_sw_setup(struct gk20a *g) } /* update calibration to fuse */ - BOARDOBJGRP_FOR_EACH(&(g->perf_pmu->volt.volt_rail_metadata. + BOARDOBJGRP_FOR_EACH(&(g->pmu->perf_pmu->volt.volt_rail_metadata. volt_rails.super), struct voltage_rail *, pvolt_rail, i) { status = volt_rail_state_init(g, pvolt_rail); @@ -455,7 +455,7 @@ int volt_rail_pmu_setup(struct gk20a *g) nvgpu_log_info(g, " "); - pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super; + pboardobjgrp = &g->pmu->perf_pmu->volt.volt_rail_metadata.volt_rails.super; if (!pboardobjgrp->bconstructed) { return -EINVAL; @@ -470,7 +470,7 @@ int volt_rail_pmu_setup(struct gk20a *g) u8 nvgpu_volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g, u8 vbios_volt_domain) { - if (g->perf_pmu->volt.volt_rail_metadata.volt_domain_hal == + if (g->pmu->perf_pmu->volt.volt_rail_metadata.volt_domain_hal == CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL) { return CTRL_VOLT_DOMAIN_LOGIC; } else { @@ -481,7 +481,7 @@ u8 nvgpu_volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g, u8 nvgpu_volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain) { - if (g->perf_pmu->volt.volt_rail_metadata.volt_domain_hal == + if (g->pmu->perf_pmu->volt.volt_rail_metadata.volt_domain_hal == CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL) { return 0U; } else { @@ -548,7 +548,7 @@ int nvgpu_volt_get_vmin_vmax_ps35(struct gk20a *g, u32 *vmin_uv, u32 *vmax_uv) return status; } - pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super; + pboardobjgrp = &g->pmu->perf_pmu->volt.volt_rail_metadata.volt_rails.super; BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) { volt_rail = (struct voltage_rail *)(void *)pboardobj; @@ -577,7 +577,7 @@ int nvgpu_volt_get_curr_volt_ps35(struct gk20a *g, u32 *vcurr_uv) return status; } - pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super; + pboardobjgrp = &g->pmu->perf_pmu->volt.volt_rail_metadata.volt_rails.super; BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) { volt_rail = (struct voltage_rail *)(void *)pboardobj; @@ -596,7 +596,7 @@ u8 nvgpu_volt_get_vmargin_ps35(struct gk20a *g) struct voltage_rail *volt_rail = NULL; u8 index, vmargin_uv; - pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super; + pboardobjgrp = &g->pmu->perf_pmu->volt.volt_rail_metadata.volt_rails.super; BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj *, pboardobj, index) { volt_rail = (struct voltage_rail *)(void *)pboardobj; diff --git a/drivers/gpu/nvgpu/hal/clk/clk_tu104.c b/drivers/gpu/nvgpu/hal/clk/clk_tu104.c index 9a8b74649..0352abcea 100644 --- a/drivers/gpu/nvgpu/hal/clk/clk_tu104.c +++ b/drivers/gpu/nvgpu/hal/clk/clk_tu104.c @@ -572,7 +572,7 @@ unsigned long tu104_clk_maxrate(struct gk20a *g, u32 api_domain) void tu104_get_change_seq_time(struct gk20a *g, s64 *change_time) { - struct change_seq_pmu *change_seq_pmu = &g->perf_pmu->changeseq_pmu; + struct change_seq_pmu *change_seq_pmu = &g->pmu->perf_pmu->changeseq_pmu; s64 diff = change_seq_pmu->stop_time - change_seq_pmu->start_time; *change_time = diff; diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 1db2ead2d..e12561db2 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -1261,7 +1261,7 @@ static const struct gpu_ops tu104_ops = { nvgpu_clk_mon_check_master_fault_status, .clk_mon_check_status = nvgpu_clk_mon_check_status, .clk_mon_init_domains = nvgpu_clk_mon_init_domains, - .perf_pmu_vfe_load = nvgpu_perf_pmu_vfe_load_ps35, + .perf_pmu_vfe_load = nvgpu_pmu_perf_load, }, #ifdef CONFIG_NVGPU_CLK_ARB .clk_arb = { @@ -1722,12 +1722,10 @@ int tu104_init_hal(struct gk20a *g) /* for now */ gops->clk.support_pmgr_domain = false; gops->clk.support_lpwr_pg = false; - gops->pmu_perf.support_changeseq = true; - gops->pmu_perf.support_vfe = true; gops->clk.support_vf_point = true; gops->clk.lut_num_entries = CTRL_CLK_LUT_NUM_ENTRIES_GV10x; #ifdef CONFIG_NVGPU_LS_PMU - gops->clk.perf_pmu_vfe_load = nvgpu_perf_pmu_vfe_load_ps35; + gops->clk.perf_pmu_vfe_load = nvgpu_pmu_perf_load; #endif #ifdef CONFIG_NVGPU_DGPU nvgpu_pramin_ops_init(g); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 1dea9b7ca..10ee7b186 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -92,7 +92,6 @@ struct nvgpu_cpu_time_correlation_sample; struct nvgpu_clk_arb; #endif struct nvgpu_setup_bind_args; -struct perf_pmupstate; struct boardobjgrp; struct boardobjgrp_pmu_cmd; struct boardobjgrpmask; @@ -394,8 +393,6 @@ struct gpu_ops { #endif struct { int (*handle_pmu_perf_event)(struct gk20a *g, void *pmu_msg); - bool support_changeseq; - bool support_vfe; } pmu_perf; #ifdef CONFIG_NVGPU_DEBUGGER struct { @@ -738,7 +735,6 @@ struct gk20a { struct nvgpu_pmu *pmu; struct nvgpu_acr *acr; struct nvgpu_ecc ecc; - struct perf_pmupstate *perf_pmu; struct pmgr_pmupstate *pmgr_pmu; struct nvgpu_sec2 sec2; diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index 4ad5eb9c5..03bd6da8a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -302,6 +302,7 @@ struct nvgpu_pmu { struct nvgpu_pmu_perfmon *pmu_perfmon; struct nvgpu_clk_pmupstate *clk_pmu; struct therm_pmupstate *therm_pmu; + struct perf_pmupstate *perf_pmu; void (*remove_support)(struct nvgpu_pmu *pmu); void (*volt_rpc_handler)(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h index c972be8ea..3fed73898 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h @@ -1,7 +1,7 @@ /* * general clock structures & definitions * - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -71,7 +71,6 @@ struct nvgpu_clk_pmupstate { /* clk_domain unit functions */ int (*get_fll)(struct gk20a *g, struct nvgpu_set_fll_clk *setfllclk); - int (*set_boot_fll)(struct gk20a *g); void (*set_p0_clks)(struct gk20a *g, u8 *gpcclk_domain, u32 *gpcclk_clkmhz, struct nvgpu_clk_slave_freq *vf_point, struct ctrl_perf_change_seq_change_input *change_input); @@ -98,7 +97,6 @@ struct nvgpu_clk_pmupstate { int nvgpu_clk_init_pmupstate(struct gk20a *g); void nvgpu_clk_free_pmupstate(struct gk20a *g); -int nvgpu_clk_set_boot_fll_clk_tu10x(struct gk20a *g); int nvgpu_clk_get_fll_clks(struct gk20a *g, struct nvgpu_set_fll_clk *setfllclk); int nvgpu_clk_domain_freq_to_volt(struct gk20a *g, u8 clkdomain_idx, diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/cmd.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/cmd.h index 141bcb901..e9f7099ca 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/cmd.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/cmd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/msg.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/msg.h index c271601f3..c19b5acea 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/msg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/msg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -30,7 +30,6 @@ #include #include #include -#include #include #include diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h index 7831a33e0..07c76fea7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h @@ -22,15 +22,10 @@ #ifndef NVGPU_PMU_PERF_H #define NVGPU_PMU_PERF_H -#include -#include -#include #include -#include #include #include #include -#include /* Dependency of this include will be removed in further CL */ #include "../../../common/pmu/perf/ucode_perf_change_seq_inf.h" @@ -42,6 +37,34 @@ struct nvgpu_clk_slave_freq; #define CTRL_PERF_PSTATE_P8 8U #define CLK_SET_INFO_MAX_SIZE (32U) +#define NV_PMU_PERF_CMD_ID_RPC (0x00000002U) +#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET (0x00000003U) +#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000004U) + +/*! + * RPC calls serviced by PERF unit. + */ +#define NV_PMU_RPC_ID_PERF_BOARD_OBJ_GRP_CMD 0x00U +#define NV_PMU_RPC_ID_PERF_LOAD 0x01U +#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_GET 0x02U +#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_SET 0x03U +#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_SET_CONTROL 0x04U +#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUEUE_CHANGE 0x05U +#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOCK 0x06U +#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUERY 0x07U +#define NV_PMU_RPC_ID_PERF_PERF_LIMITS_INVALIDATE 0x08U +#define NV_PMU_RPC_ID_PERF_PERF_PSTATE_STATUS_UPDATE 0x09U +#define NV_PMU_RPC_ID_PERF_VFE_EQU_EVAL 0x0AU +#define NV_PMU_RPC_ID_PERF_VFE_INVALIDATE 0x0BU +#define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_SET 0x0CU +#define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_GET 0x0DU +#define NV_PMU_RPC_ID_PERF__COUNT 0x0EU + +/* PERF Message-type Definitions */ +#define NV_PMU_PERF_MSG_ID_RPC (0x00000003U) +#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004U) +#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006U) + struct nvgpu_vfe_invalidate { bool state_change; struct nvgpu_cond wq; @@ -107,36 +130,27 @@ struct perf_pmupstate { struct vfe_equs vfe_equobjs; struct pstates pstatesobjs; struct nvgpu_pmu_volt volt; - struct obj_lwpr lpwr; struct nvgpu_vfe_invalidate vfe_init; struct change_seq_pmu changeseq_pmu; }; -int nvgpu_perf_pmu_init_pmupstate(struct gk20a *g); -void nvgpu_perf_pmu_free_pmupstate(struct gk20a *g); -int nvgpu_perf_pmu_vfe_load_ps35(struct gk20a *g); +int nvgpu_pmu_perf_init(struct gk20a *g); +void nvgpu_pmu_perf_deinit(struct gk20a *g); +int nvgpu_pmu_perf_sw_setup(struct gk20a *g); +int nvgpu_pmu_perf_pmu_setup(struct gk20a *g); -int nvgpu_vfe_equ_sw_setup(struct gk20a *g); -int nvgpu_vfe_equ_pmu_setup(struct gk20a *g); +int nvgpu_pmu_perf_load(struct gk20a *g); -int nvgpu_vfe_var_sw_setup(struct gk20a *g); -int nvgpu_vfe_var_pmu_setup(struct gk20a *g); -int nvgpu_vfe_var_get_s_param(struct gk20a *g, u64 *s_param); +int nvgpu_pmu_perf_vfe_get_s_param(struct gk20a *g, u64 *s_param); -int nvgpu_vfe_get_volt_margin_limit(struct gk20a *g, u32 *vmargin_uv); -int nvgpu_vfe_get_freq_margin_limit(struct gk20a *g, u32 *fmargin_mhz); +int nvgpu_pmu_perf_vfe_get_volt_margin(struct gk20a *g, u32 *vmargin_uv); +int nvgpu_pmu_perf_vfe_get_freq_margin(struct gk20a *g, u32 *fmargin_mhz); -int nvgpu_perf_change_seq_sw_setup(struct gk20a *g); -int nvgpu_perf_change_seq_pmu_setup(struct gk20a *g); -int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, +int nvgpu_pmu_perf_changeseq_set_clks(struct gk20a *g, struct nvgpu_clk_slave_freq *vf_point); -int nvgpu_perf_pstate_get_lpwr_index(struct gk20a *g, u32 num, u8 *lpwr_idx); -int nvgpu_get_pstate_entry_idx(struct gk20a *g, u32 num); struct clk_set_info *nvgpu_pmu_perf_pstate_get_clk_set_info(struct gk20a *g, u32 pstate_num, u32 clkwhich); -int nvgpu_pmu_perf_pstate_sw_setup(struct gk20a *g); -int nvgpu_pmu_perf_pstate_pmu_setup(struct gk20a *g); #endif /* NVGPU_PMU_PERF_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/perf.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/perf.h deleted file mode 100644 index f439681d9..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/perf.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_PMUIF_PERF_H -#define NVGPU_PMUIF_PERF_H - -#include "volt.h" - -#define NV_PMU_PERF_CMD_ID_RPC (0x00000002U) -#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET (0x00000003U) -#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000004U) - -/*! - * RPC calls serviced by PERF unit. - */ -#define NV_PMU_RPC_ID_PERF_BOARD_OBJ_GRP_CMD 0x00U -#define NV_PMU_RPC_ID_PERF_LOAD 0x01U -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_GET 0x02U -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_SET 0x03U -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_SET_CONTROL 0x04U -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUEUE_CHANGE 0x05U -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOCK 0x06U -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUERY 0x07U -#define NV_PMU_RPC_ID_PERF_PERF_LIMITS_INVALIDATE 0x08U -#define NV_PMU_RPC_ID_PERF_PERF_PSTATE_STATUS_UPDATE 0x09U -#define NV_PMU_RPC_ID_PERF_VFE_EQU_EVAL 0x0AU -#define NV_PMU_RPC_ID_PERF_VFE_INVALIDATE 0x0BU -#define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_SET 0x0CU -#define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_GET 0x0DU -#define NV_PMU_RPC_ID_PERF__COUNT 0x0EU -/* - * Defines the structure that holds data - * used to execute LOAD RPC. - */ -struct nv_pmu_rpc_struct_perf_load { - /* [IN/OUT] Must be first field in RPC structure */ - struct nv_pmu_rpc_header hdr; - bool b_load; - u32 scratch[1]; -}; - -/* PERF Message-type Definitions */ -#define NV_PMU_PERF_MSG_ID_RPC (0x00000003U) -#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004U) -#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006U) - -/* PERF RPC ID Definitions */ -#define NV_PMU_RPC_ID_PERF_VFE_CALLBACK 0x01U -#define NV_PMU_RPC_ID_PERF_SEQ_COMPLETION 0x02U -#define NV_PMU_RPC_ID_PERF_PSTATES_INVALIDATE 0x03U - -/* - * Simply a union of all specific PERF messages. Forms the general packet - * exchanged between the Kernel and PMU when sending and receiving PERF messages - * (respectively). - */ - -struct pmu_nvgpu_rpc_perf_event { - struct pmu_hdr msg_hdr; - struct pmu_nvgpu_rpc_header rpc_hdr; -}; - -#endif /* NVGPU_PMUIF_PERF_H */ diff --git a/drivers/gpu/nvgpu/os/linux/debug_s_param.c b/drivers/gpu/nvgpu/os/linux/debug_s_param.c index 150430e28..058a35741 100644 --- a/drivers/gpu/nvgpu/os/linux/debug_s_param.c +++ b/drivers/gpu/nvgpu/os/linux/debug_s_param.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -25,7 +25,7 @@ static int get_s_param_info(void *data, u64 *val) struct gk20a *g = (struct gk20a *)data; int status = 0; - status = nvgpu_vfe_var_get_s_param(g, val); + status = nvgpu_pmu_perf_vfe_get_s_param(g, val); if(status != 0) { nvgpu_err(g, "Vfe_var get s_param failed"); return status;