gpu: nvgpu: define uapi for register buffer ioctl

To enable userspace query about comptags allocation status of a buffer,
comptags are to be allocated only during buffer allocation through
nvrm_gpu. Further, other metadata can be associated with the
buffer during allocation.

Define a new ioctl NVGPU_GPU_IOCTL_REGISTER_BUFFER and related input
struct for this purpose.

Define GPU characteristics flag to indicate support of buffer metadata.

Bug 200586313

Change-Id: I0be8b0bf1fbbf1be2746ffe46aa929e414d3ac36
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2481882
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sagar Kamble
2021-02-08 15:41:29 +05:30
committed by mobile promotions
parent 8d6b654afb
commit 7e7d36f8e5

View File

@@ -182,6 +182,8 @@ struct nvgpu_gpu_zbc_query_table_args {
#define NVGPU_GPU_FLAGS_SUPPORT_SMPC_GLOBAL_MODE (1ULL << 48) #define NVGPU_GPU_FLAGS_SUPPORT_SMPC_GLOBAL_MODE (1ULL << 48)
/* Retrieving contents of graphics context is supported */ /* Retrieving contents of graphics context is supported */
#define NVGPU_GPU_FLAGS_SUPPORT_GET_GR_CONTEXT (1ULL << 49) #define NVGPU_GPU_FLAGS_SUPPORT_GET_GR_CONTEXT (1ULL << 49)
/* Additional buffer metadata association supported */
#define NVGPU_GPU_FLAGS_SUPPORT_BUFFER_METADATA (1ULL << 50)
/* SM LRF ECC is enabled */ /* SM LRF ECC is enabled */
#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60) #define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60)
/* SM SHM ECC is enabled */ /* SM SHM ECC is enabled */
@@ -902,6 +904,76 @@ struct nvgpu_gpu_set_deterministic_opts_args {
__u64 channels; /* in */ __u64 channels; /* in */
}; };
/*
* NVGPU_GPU_COMPTAGS_ALLOC_NONE: Specified to not allocate comptags
* for the buffer.
*/
#define NVGPU_GPU_COMPTAGS_ALLOC_NONE 0U
/*
* NVGPU_GPU_COMPTAGS_ALLOC_REQUESTED: Specified to attempt comptags
* allocation for the buffer. If comptags are not available, the
* register buffer call will not fail and userspace can fallback
* to no compression.
*/
#define NVGPU_GPU_COMPTAGS_ALLOC_REQUESTED 1U
/*
* NVGPU_GPU_COMPTAGS_ALLOC_REQUIRED: Specified to allocate comptags
* for the buffer when userspace can't fallback to no compression.
* If comptags are not available, the register buffer call will fail.
*/
#define NVGPU_GPU_COMPTAGS_ALLOC_REQUIRED 2U
/*
* If the comptags are allocated for the buffer, this flag is set in the output
* flags in the register buffer ioctl.
*/
#define NVGPU_GPU_REGISTER_BUFFER_FLAGS_COMPTAGS_ALLOCATED (1U << 0)
/* Maximum size of the user supplied buffer metadata */
#define NVGPU_GPU_REGISTER_BUFFER_METADATA_MAX_SIZE 256U
/*
* REGISTER_BUFFER ioctl is supported when the enabled flag
* NVGPU_GPU_FLAGS_SUPPORT_BUFFER_METADATA is set. It will
* return -EINVAL if that enabled flag isn't enabled.
*/
struct nvgpu_gpu_register_buffer_args {
/* [in] dmabuf fd */
__s32 dmabuf_fd;
/*
* [in] Compression tags allocation control.
*
* Set to one of the NVGPU_GPU_COMPTAGS_ALLOC_* values. See the
* description of the values for semantics of this field.
*/
__u8 comptags_alloc_control;
__u8 reserved0;
__u16 reserved1;
/*
* [in] Pointer to buffer metadata.
*
* This is a binary blob populated by nvrm_gpu that will be associated
* with the dmabuf.
*/
__u64 metadata_addr;
/* [in] buffer metadata size */
__u32 metadata_size;
/*
* [out] flags.
*
* See description of NVGPU_GPU_REGISTER_BUFFER_FLAGS_* for semantics
* of this field.
*/
__u32 flags;
};
#define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \ #define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \
_IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args) _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args)
#define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \ #define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \
@@ -985,8 +1057,10 @@ struct nvgpu_gpu_set_deterministic_opts_args {
#define NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS \ #define NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS \
_IOWR(NVGPU_GPU_IOCTL_MAGIC, 40, \ _IOWR(NVGPU_GPU_IOCTL_MAGIC, 40, \
struct nvgpu_gpu_set_deterministic_opts_args) struct nvgpu_gpu_set_deterministic_opts_args)
#define NVGPU_GPU_IOCTL_REGISTER_BUFFER \
_IOWR(NVGPU_GPU_IOCTL_MAGIC, 41, struct nvgpu_gpu_register_buffer_args)
#define NVGPU_GPU_IOCTL_LAST \ #define NVGPU_GPU_IOCTL_LAST \
_IOC_NR(NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS) _IOC_NR(NVGPU_GPU_IOCTL_REGISTER_BUFFER)
#define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \ #define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \
sizeof(struct nvgpu_gpu_get_cpu_time_correlation_info_args) sizeof(struct nvgpu_gpu_get_cpu_time_correlation_info_args)