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gpu: nvgpu: Remove cyclic dependency PMU<->GR.

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-Created & used HAL for dumping gr falcon stats.
-Trimmed the fecs_dump_falcon_stats to re-use code from
 generic falcon debug dump.

JIRA NVGPU-621

Change-Id: Ia008726915112b33f0aca68a48cb98b8ed2c3475
Signed-off-by: Deepak <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1923353
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak
2018-10-10 13:00:49 +05:30
committed by mobile promotions
parent 435892a784
commit 7e8ca5f5e7
11 changed files with 19 additions and 80 deletions
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4
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
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@@ -1409,7 +1409,7 @@ static void gk20a_fifo_handle_chsw_fault(struct gk20a *g)
intr = gk20a_readl(g, fifo_intr_chsw_error_r());
nvgpu_err(g, "chsw: %08x", intr);
gk20a_fecs_dump_falcon_stats(g);
g->ops.gr.dump_gr_falcon_stats(g);
gk20a_writel(g, fifo_intr_chsw_error_r(), intr);
}
@@ -1722,7 +1722,7 @@ static bool gk20a_fifo_handle_mmu_fault_locked(
mmfault_info.access_type, mmfault_info.inst_ptr);
if (ctxsw) {
gk20a_fecs_dump_falcon_stats(g);
g->ops.gr.dump_gr_falcon_stats(g);
nvgpu_err(g, "gr_status_r : 0x%x",
gk20a_readl(g, gr_status_r()));
}