diff --git a/drivers/gpu/nvgpu/common/fifo/channel.c b/drivers/gpu/nvgpu/common/fifo/channel.c index ad1f0ecba..27e02ca22 100644 --- a/drivers/gpu/nvgpu/common/fifo/channel.c +++ b/drivers/gpu/nvgpu/common/fifo/channel.c @@ -403,8 +403,8 @@ static void gk20a_free_channel(struct channel_gk20a *ch, bool force) timeout); #ifdef CONFIG_GK20A_CTXSW_TRACE - if (g->ops.fecs_trace.unbind_channel && !ch->vpr) - g->ops.fecs_trace.unbind_channel(g, &ch->inst_block); + if (g->ops.gr.fecs_trace.unbind_channel && !ch->vpr) + g->ops.gr.fecs_trace.unbind_channel(g, &ch->inst_block); #endif if (g->ops.fifo.free_channel_ctx_header != NULL) { diff --git a/drivers/gpu/nvgpu/common/gr/fecs_trace/fecs_trace.c b/drivers/gpu/nvgpu/common/gr/fecs_trace/fecs_trace.c index 68f1b158e..fdfa10321 100644 --- a/drivers/gpu/nvgpu/common/gr/fecs_trace/fecs_trace.c +++ b/drivers/gpu/nvgpu/common/gr/fecs_trace/fecs_trace.c @@ -265,11 +265,11 @@ int nvgpu_gr_fecs_trace_enable(struct gk20a *g) if (trace->enable_count == 1U) { /* drop data in hw buffer */ - if (g->ops.fecs_trace.flush) - g->ops.fecs_trace.flush(g); + if (g->ops.gr.fecs_trace.flush) + g->ops.gr.fecs_trace.flush(g); - write = g->ops.fecs_trace.get_write_index(g); - g->ops.fecs_trace.set_read_index(g, write); + write = g->ops.gr.fecs_trace.get_write_index(g); + g->ops.gr.fecs_trace.set_read_index(g, write); err = nvgpu_thread_create(&trace->poll_task, g, nvgpu_gr_fecs_trace_periodic_polling, __func__); @@ -313,8 +313,8 @@ void nvgpu_gr_fecs_trace_reset_buffer(struct gk20a *g) { nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, " "); - g->ops.fecs_trace.set_read_index(g, - g->ops.fecs_trace.get_write_index(g)); + g->ops.gr.fecs_trace.set_read_index(g, + g->ops.gr.fecs_trace.get_write_index(g)); } /* @@ -427,16 +427,16 @@ int nvgpu_gr_fecs_trace_ring_read(struct gk20a *g, int index, if (!entry.context_id) continue; - if (g->ops.fecs_trace.vm_dev_write != NULL) { - g->ops.fecs_trace.vm_dev_write(g, entry.vmid, + if (g->ops.gr.fecs_trace.vm_dev_write != NULL) { + g->ops.gr.fecs_trace.vm_dev_write(g, entry.vmid, vm_update_mask, &entry); } else { - gk20a_ctxsw_trace_write(g, &entry); + nvgpu_gr_fecs_trace_write_entry(g, &entry); } count++; } - gk20a_ctxsw_trace_wake_up(g, vmid); + nvgpu_gr_fecs_trace_wake_up(g, vmid); return count; } @@ -459,7 +459,7 @@ int nvgpu_gr_fecs_trace_poll(struct gk20a *g) goto done_unlock; } - write = g->ops.fecs_trace.get_write_index(g); + write = g->ops.gr.fecs_trace.get_write_index(g); if ((write < 0) || (write >= GK20A_FECS_TRACE_NUM_RECORDS)) { nvgpu_err(g, "failed to acquire write index, write=%d", write); @@ -467,7 +467,7 @@ int nvgpu_gr_fecs_trace_poll(struct gk20a *g) goto done; } - read = g->ops.fecs_trace.get_read_index(g); + read = g->ops.gr.fecs_trace.get_read_index(g); cnt = CIRC_CNT(write, read, GK20A_FECS_TRACE_NUM_RECORDS); if (!cnt) @@ -475,7 +475,7 @@ int nvgpu_gr_fecs_trace_poll(struct gk20a *g) nvgpu_log(g, gpu_dbg_ctxsw, "circular buffer: read=%d (mailbox=%d) write=%d cnt=%d", - read, g->ops.fecs_trace.get_read_index(g), write, cnt); + read, g->ops.gr.fecs_trace.get_read_index(g), write, cnt); /* Ensure all FECS writes have made it to SYSMEM */ g->ops.mm.fb_flush(g); @@ -492,7 +492,7 @@ int nvgpu_gr_fecs_trace_poll(struct gk20a *g) /* ensure FECS records has been updated before incrementing read index */ nvgpu_wmb(); - g->ops.fecs_trace.set_read_index(g, read); + g->ops.gr.fecs_trace.set_read_index(g, read); /* * FECS ucode does a priv holdoff around the assertion of context @@ -500,13 +500,13 @@ int nvgpu_gr_fecs_trace_poll(struct gk20a *g) * fail due to this. Hence, do write with ack i.e. write and read * it back to make sure write happened for mailbox1. */ - while (g->ops.fecs_trace.get_read_index(g) != read) { + while (g->ops.gr.fecs_trace.get_read_index(g) != read) { nvgpu_log(g, gpu_dbg_ctxsw, "mailbox1 update failed"); - g->ops.fecs_trace.set_read_index(g, read); + g->ops.gr.fecs_trace.set_read_index(g, read); } - if (g->ops.fecs_trace.vm_dev_update) { - g->ops.fecs_trace.vm_dev_update(g, vm_update_mask); + if (g->ops.gr.fecs_trace.vm_dev_update) { + g->ops.gr.fecs_trace.vm_dev_update(g, vm_update_mask); } done: @@ -539,11 +539,11 @@ int nvgpu_gr_fecs_trace_reset(struct gk20a *g) { nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, " "); - if (!g->ops.fecs_trace.is_enabled(g)) + if (!g->ops.gr.fecs_trace.is_enabled(g)) return 0; nvgpu_gr_fecs_trace_poll(g); - return g->ops.fecs_trace.set_read_index(g, 0); + return g->ops.gr.fecs_trace.set_read_index(g, 0); } static u32 nvgpu_gr_fecs_trace_fecs_context_ptr(struct gk20a *g, @@ -634,9 +634,9 @@ int nvgpu_gr_fecs_trace_unbind_channel(struct gk20a *g, nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, "context_ptr=%x", context_ptr); - if (g->ops.fecs_trace.is_enabled(g)) { - if (g->ops.fecs_trace.flush) { - g->ops.fecs_trace.flush(g); + if (g->ops.gr.fecs_trace.is_enabled(g)) { + if (g->ops.gr.fecs_trace.flush) { + g->ops.gr.fecs_trace.flush(g); } nvgpu_gr_fecs_trace_poll(g); } diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index 508d5f5ca..d4b7b7ad5 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -307,7 +307,28 @@ static const struct gpu_ops vgpu_gp10b_ops = { .add_stencil = NULL, .get_gpcs_swdx_dss_zbc_c_format_reg = NULL, .get_gpcs_swdx_dss_zbc_z_format_reg = NULL, - } + }, +#ifdef CONFIG_GK20A_CTXSW_TRACE + .fecs_trace = { + .alloc_user_buffer = vgpu_alloc_user_buffer, + .free_user_buffer = vgpu_free_user_buffer, + .mmap_user_buffer = vgpu_mmap_user_buffer, + .init = vgpu_fecs_trace_init, + .deinit = vgpu_fecs_trace_deinit, + .enable = vgpu_fecs_trace_enable, + .disable = vgpu_fecs_trace_disable, + .is_enabled = vgpu_fecs_trace_is_enabled, + .reset = NULL, + .flush = NULL, + .poll = vgpu_fecs_trace_poll, + .bind_channel = NULL, + .unbind_channel = NULL, + .max_entries = vgpu_fecs_trace_max_entries, + .set_filter = vgpu_fecs_trace_set_filter, + .get_buffer_full_mailbox_val = + gm20b_fecs_trace_get_buffer_full_mailbox_val, + }, +#endif /* CONFIG_GK20A_CTXSW_TRACE */ }, .perf = { .get_pmm_per_chiplet_offset = @@ -459,27 +480,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_netlist_name = gp10b_netlist_get_name, .is_fw_defined = gp10b_netlist_is_firmware_defined, }, -#ifdef CONFIG_GK20A_CTXSW_TRACE - .fecs_trace = { - .alloc_user_buffer = vgpu_alloc_user_buffer, - .free_user_buffer = vgpu_free_user_buffer, - .mmap_user_buffer = vgpu_mmap_user_buffer, - .init = vgpu_fecs_trace_init, - .deinit = vgpu_fecs_trace_deinit, - .enable = vgpu_fecs_trace_enable, - .disable = vgpu_fecs_trace_disable, - .is_enabled = vgpu_fecs_trace_is_enabled, - .reset = NULL, - .flush = NULL, - .poll = vgpu_fecs_trace_poll, - .bind_channel = NULL, - .unbind_channel = NULL, - .max_entries = vgpu_fecs_trace_max_entries, - .set_filter = vgpu_fecs_trace_set_filter, - .get_buffer_full_mailbox_val = - gm20b_fecs_trace_get_buffer_full_mailbox_val, - }, -#endif /* CONFIG_GK20A_CTXSW_TRACE */ .mm = { .gmmu_map = vgpu_locked_gmmu_map, .gmmu_unmap = vgpu_locked_gmmu_unmap, @@ -694,9 +694,6 @@ int vgpu_gp10b_init_hal(struct gk20a *g) gops->engine_status = vgpu_gp10b_ops.engine_status; gops->pbdma_status = vgpu_gp10b_ops.pbdma_status; gops->netlist = vgpu_gp10b_ops.netlist; -#ifdef CONFIG_GK20A_CTXSW_TRACE - gops->fecs_trace = vgpu_gp10b_ops.fecs_trace; -#endif gops->mm = vgpu_gp10b_ops.mm; gops->pramin = vgpu_gp10b_ops.pramin; gops->therm = vgpu_gp10b_ops.therm; diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index 867ac72a6..01f927f23 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -355,7 +355,28 @@ static const struct gpu_ops vgpu_gv11b_ops = { .hwpm_map = { .align_regs_perf_pma = gv100_gr_hwpm_map_align_regs_perf_pma, - } + }, +#ifdef CONFIG_GK20A_CTXSW_TRACE + .fecs_trace = { + .alloc_user_buffer = vgpu_alloc_user_buffer, + .free_user_buffer = vgpu_free_user_buffer, + .mmap_user_buffer = vgpu_mmap_user_buffer, + .init = vgpu_fecs_trace_init, + .deinit = vgpu_fecs_trace_deinit, + .enable = vgpu_fecs_trace_enable, + .disable = vgpu_fecs_trace_disable, + .is_enabled = vgpu_fecs_trace_is_enabled, + .reset = NULL, + .flush = NULL, + .poll = vgpu_fecs_trace_poll, + .bind_channel = NULL, + .unbind_channel = NULL, + .max_entries = vgpu_fecs_trace_max_entries, + .set_filter = vgpu_fecs_trace_set_filter, + .get_buffer_full_mailbox_val = + gv11b_fecs_trace_get_buffer_full_mailbox_val, + }, +#endif /* CONFIG_GK20A_CTXSW_TRACE */ }, .perf = { .get_pmm_per_chiplet_offset = @@ -537,27 +558,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_netlist_name = gv11b_netlist_get_name, .is_fw_defined = gv11b_netlist_is_firmware_defined, }, -#ifdef CONFIG_GK20A_CTXSW_TRACE - .fecs_trace = { - .alloc_user_buffer = vgpu_alloc_user_buffer, - .free_user_buffer = vgpu_free_user_buffer, - .mmap_user_buffer = vgpu_mmap_user_buffer, - .init = vgpu_fecs_trace_init, - .deinit = vgpu_fecs_trace_deinit, - .enable = vgpu_fecs_trace_enable, - .disable = vgpu_fecs_trace_disable, - .is_enabled = vgpu_fecs_trace_is_enabled, - .reset = NULL, - .flush = NULL, - .poll = vgpu_fecs_trace_poll, - .bind_channel = NULL, - .unbind_channel = NULL, - .max_entries = vgpu_fecs_trace_max_entries, - .set_filter = vgpu_fecs_trace_set_filter, - .get_buffer_full_mailbox_val = - gv11b_fecs_trace_get_buffer_full_mailbox_val, - }, -#endif /* CONFIG_GK20A_CTXSW_TRACE */ .mm = { .gmmu_map = vgpu_locked_gmmu_map, .gmmu_unmap = vgpu_locked_gmmu_unmap, @@ -775,9 +775,6 @@ int vgpu_gv11b_init_hal(struct gk20a *g) gops->pbdma_status = vgpu_gv11b_ops.pbdma_status; gops->netlist = vgpu_gv11b_ops.netlist; gops->mm = vgpu_gv11b_ops.mm; -#ifdef CONFIG_GK20A_CTXSW_TRACE - gops->fecs_trace = vgpu_gv11b_ops.fecs_trace; -#endif gops->therm = vgpu_gv11b_ops.therm; gops->pmu = vgpu_gv11b_ops.pmu; gops->clk_arb = vgpu_gv11b_ops.clk_arb; diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index f4af9eb51..473dfccff 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -653,8 +653,8 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) * Resetting engine will alter read/write index. Need to flush * circular buffer before re-enabling FECS. */ - if (g->ops.fecs_trace.reset) - g->ops.fecs_trace.reset(g); + if (g->ops.gr.fecs_trace.reset) + g->ops.gr.fecs_trace.reset(g); #endif if (!nvgpu_platform_is_simulation(g)) { /*HALT_PIPELINE method, halt GR engine*/ @@ -975,7 +975,7 @@ static bool gk20a_fifo_handle_mmu_fault_locked( #ifdef CONFIG_GK20A_CTXSW_TRACE if (tsg != NULL) { - gk20a_ctxsw_trace_tsg_reset(g, tsg); + nvgpu_gr_fecs_trace_add_tsg_reset(g, tsg); } #endif /* diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index ce0e27b1f..bf6552680 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -2099,8 +2099,8 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) } #ifdef CONFIG_GK20A_CTXSW_TRACE - if (g->ops.fecs_trace.bind_channel && !c->vpr) { - err = g->ops.fecs_trace.bind_channel(g, &c->inst_block, + if (g->ops.gr.fecs_trace.bind_channel && !c->vpr) { + err = g->ops.gr.fecs_trace.bind_channel(g, &c->inst_block, c->subctx, gr_ctx, tsg->tgid, 0); if (err != 0) { nvgpu_warn(g, @@ -2121,8 +2121,8 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) goto out; } #ifdef CONFIG_GK20A_CTXSW_TRACE - if (g->ops.fecs_trace.bind_channel && !c->vpr) { - err = g->ops.fecs_trace.bind_channel(g, &c->inst_block, + if (g->ops.gr.fecs_trace.bind_channel && !c->vpr) { + err = g->ops.gr.fecs_trace.bind_channel(g, &c->inst_block, c->subctx, gr_ctx, tsg->tgid, 0); if (err != 0) { nvgpu_warn(g, @@ -3296,7 +3296,7 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch, #ifdef CONFIG_GK20A_CTXSW_TRACE if (mailbox_value == - g->ops.fecs_trace.get_buffer_full_mailbox_val()) { + g->ops.gr.fecs_trace.get_buffer_full_mailbox_val()) { nvgpu_info(g, "ctxsw intr0 set by ucode, " "timestamp buffer full"); nvgpu_gr_fecs_trace_reset_buffer(g); diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index a07c3171e..71814d3ad 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -460,6 +460,29 @@ static const struct gpu_ops gp10b_ops = { .get_pd_dist_skip_table_size = gm20b_gr_config_get_pd_dist_skip_table_size, }, +#ifdef CONFIG_GK20A_CTXSW_TRACE + .fecs_trace = { + .alloc_user_buffer = nvgpu_gr_fecs_trace_ring_alloc, + .free_user_buffer = nvgpu_gr_fecs_trace_ring_free, + .mmap_user_buffer = nvgpu_gr_fecs_trace_mmap_buffer, + .init = nvgpu_gr_fecs_trace_init, + .deinit = nvgpu_gr_fecs_trace_deinit, + .enable = nvgpu_gr_fecs_trace_enable, + .disable = nvgpu_gr_fecs_trace_disable, + .is_enabled = nvgpu_gr_fecs_trace_is_enabled, + .reset = nvgpu_gr_fecs_trace_reset, + .flush = gp10b_fecs_trace_flush, + .poll = nvgpu_gr_fecs_trace_poll, + .bind_channel = nvgpu_gr_fecs_trace_bind_channel, + .unbind_channel = nvgpu_gr_fecs_trace_unbind_channel, + .max_entries = nvgpu_gr_fecs_trace_max_entries, + .get_buffer_full_mailbox_val = + gm20b_fecs_trace_get_buffer_full_mailbox_val, + .get_read_index = gm20b_fecs_trace_get_read_index, + .get_write_index = gm20b_fecs_trace_get_write_index, + .set_read_index = gm20b_fecs_trace_set_read_index, + }, +#endif /* CONFIG_GK20A_CTXSW_TRACE */ .zbc = { .add_color = gp10b_gr_zbc_add_color, .add_depth = gp10b_gr_zbc_add_depth, @@ -671,29 +694,6 @@ static const struct gpu_ops gp10b_ops = { .get_netlist_name = gp10b_netlist_get_name, .is_fw_defined = gp10b_netlist_is_firmware_defined, }, -#ifdef CONFIG_GK20A_CTXSW_TRACE - .fecs_trace = { - .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc, - .free_user_buffer = gk20a_ctxsw_dev_ring_free, - .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer, - .init = nvgpu_gr_fecs_trace_init, - .deinit = nvgpu_gr_fecs_trace_deinit, - .enable = nvgpu_gr_fecs_trace_enable, - .disable = nvgpu_gr_fecs_trace_disable, - .is_enabled = nvgpu_gr_fecs_trace_is_enabled, - .reset = nvgpu_gr_fecs_trace_reset, - .flush = gp10b_fecs_trace_flush, - .poll = nvgpu_gr_fecs_trace_poll, - .bind_channel = nvgpu_gr_fecs_trace_bind_channel, - .unbind_channel = nvgpu_gr_fecs_trace_unbind_channel, - .max_entries = nvgpu_gr_fecs_trace_max_entries, - .get_buffer_full_mailbox_val = - gm20b_fecs_trace_get_buffer_full_mailbox_val, - .get_read_index = gm20b_fecs_trace_get_read_index, - .get_write_index = gm20b_fecs_trace_get_write_index, - .set_read_index = gm20b_fecs_trace_set_read_index, - }, -#endif /* CONFIG_GK20A_CTXSW_TRACE */ .mm = { .gmmu_map = gk20a_locked_gmmu_map, .gmmu_unmap = gk20a_locked_gmmu_unmap, @@ -962,9 +962,6 @@ int gp10b_init_hal(struct gk20a *g) gops->engine_status = gp10b_ops.engine_status; gops->pbdma_status = gp10b_ops.pbdma_status; gops->netlist = gp10b_ops.netlist; -#ifdef CONFIG_GK20A_CTXSW_TRACE - gops->fecs_trace = gp10b_ops.fecs_trace; -#endif gops->mm = gp10b_ops.mm; gops->pramin = gp10b_ops.pramin; gops->therm = gp10b_ops.therm; diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 4659af58a..ed73c37aa 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -589,6 +589,29 @@ static const struct gpu_ops gv100_ops = { .get_pd_dist_skip_table_size = gm20b_gr_config_get_pd_dist_skip_table_size, }, +#ifdef CONFIG_GK20A_CTXSW_TRACE + .fecs_trace = { + .alloc_user_buffer = nvgpu_gr_fecs_trace_ring_alloc, + .free_user_buffer = nvgpu_gr_fecs_trace_ring_free, + .mmap_user_buffer = nvgpu_gr_fecs_trace_mmap_buffer, + .init = nvgpu_gr_fecs_trace_init, + .deinit = nvgpu_gr_fecs_trace_deinit, + .enable = nvgpu_gr_fecs_trace_enable, + .disable = nvgpu_gr_fecs_trace_disable, + .is_enabled = nvgpu_gr_fecs_trace_is_enabled, + .reset = nvgpu_gr_fecs_trace_reset, + .flush = NULL, + .poll = nvgpu_gr_fecs_trace_poll, + .bind_channel = nvgpu_gr_fecs_trace_bind_channel, + .unbind_channel = nvgpu_gr_fecs_trace_unbind_channel, + .max_entries = nvgpu_gr_fecs_trace_max_entries, + .get_buffer_full_mailbox_val = + gm20b_fecs_trace_get_buffer_full_mailbox_val, + .get_read_index = gm20b_fecs_trace_get_read_index, + .get_write_index = gm20b_fecs_trace_get_write_index, + .set_read_index = gm20b_fecs_trace_set_read_index, + }, +#endif /* CONFIG_GK20A_CTXSW_TRACE */ .zbc = { .add_color = gp10b_gr_zbc_add_color, .add_depth = gp10b_gr_zbc_add_depth, @@ -845,29 +868,6 @@ static const struct gpu_ops gv100_ops = { .get_netlist_name = gv100_netlist_get_name, .is_fw_defined = gv100_netlist_is_firmware_defined, }, -#ifdef CONFIG_GK20A_CTXSW_TRACE - .fecs_trace = { - .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc, - .free_user_buffer = gk20a_ctxsw_dev_ring_free, - .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer, - .init = nvgpu_gr_fecs_trace_init, - .deinit = nvgpu_gr_fecs_trace_deinit, - .enable = nvgpu_gr_fecs_trace_enable, - .disable = nvgpu_gr_fecs_trace_disable, - .is_enabled = nvgpu_gr_fecs_trace_is_enabled, - .reset = nvgpu_gr_fecs_trace_reset, - .flush = NULL, - .poll = nvgpu_gr_fecs_trace_poll, - .bind_channel = nvgpu_gr_fecs_trace_bind_channel, - .unbind_channel = nvgpu_gr_fecs_trace_unbind_channel, - .max_entries = nvgpu_gr_fecs_trace_max_entries, - .get_buffer_full_mailbox_val = - gm20b_fecs_trace_get_buffer_full_mailbox_val, - .get_read_index = gm20b_fecs_trace_get_read_index, - .get_write_index = gm20b_fecs_trace_get_write_index, - .set_read_index = gm20b_fecs_trace_set_read_index, - }, -#endif /* CONFIG_GK20A_CTXSW_TRACE */ .mm = { .gmmu_map = gk20a_locked_gmmu_map, .gmmu_unmap = gk20a_locked_gmmu_unmap, @@ -1243,9 +1243,6 @@ int gv100_init_hal(struct gk20a *g) gops->pbdma_status = gv100_ops.pbdma_status; gops->netlist = gv100_ops.netlist; gops->mm = gv100_ops.mm; -#ifdef CONFIG_GK20A_CTXSW_TRACE - gops->fecs_trace = gv100_ops.fecs_trace; -#endif gops->pramin = gv100_ops.pramin; gops->therm = gv100_ops.therm; gops->pmu = gv100_ops.pmu; diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 6294e7100..30b0a246a 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -856,7 +856,7 @@ static void gv11b_fifo_locked_abort_runlist_active_tsgs(struct gk20a *g, gv11b_reset_faulted_tsg(tsg, true, true); #ifdef CONFIG_GK20A_CTXSW_TRACE - gk20a_ctxsw_trace_tsg_reset(g, tsg); + nvgpu_gr_fecs_trace_add_tsg_reset(g, tsg); #endif if (!g->fifo.deferred_reset_pending) { if (rc_type == RC_TYPE_MMU_FAULT) { @@ -1097,7 +1097,7 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, #ifdef CONFIG_GK20A_CTXSW_TRACE if (tsg != NULL) - gk20a_ctxsw_trace_tsg_reset(g, tsg); + nvgpu_gr_fecs_trace_add_tsg_reset(g, tsg); #endif if (tsg != NULL) { if (deferred_reset_pending) { diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index beee5e3d8..261df8c25 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -549,6 +549,29 @@ static const struct gpu_ops gv11b_ops = { .get_pd_dist_skip_table_size = gm20b_gr_config_get_pd_dist_skip_table_size, }, +#ifdef CONFIG_GK20A_CTXSW_TRACE + .fecs_trace = { + .alloc_user_buffer = nvgpu_gr_fecs_trace_ring_alloc, + .free_user_buffer = nvgpu_gr_fecs_trace_ring_free, + .mmap_user_buffer = nvgpu_gr_fecs_trace_mmap_buffer, + .init = nvgpu_gr_fecs_trace_init, + .deinit = nvgpu_gr_fecs_trace_deinit, + .enable = nvgpu_gr_fecs_trace_enable, + .disable = nvgpu_gr_fecs_trace_disable, + .is_enabled = nvgpu_gr_fecs_trace_is_enabled, + .reset = nvgpu_gr_fecs_trace_reset, + .flush = NULL, + .poll = nvgpu_gr_fecs_trace_poll, + .bind_channel = nvgpu_gr_fecs_trace_bind_channel, + .unbind_channel = nvgpu_gr_fecs_trace_unbind_channel, + .max_entries = nvgpu_gr_fecs_trace_max_entries, + .get_buffer_full_mailbox_val = + gv11b_fecs_trace_get_buffer_full_mailbox_val, + .get_read_index = gm20b_fecs_trace_get_read_index, + .get_write_index = gm20b_fecs_trace_get_write_index, + .set_read_index = gm20b_fecs_trace_set_read_index, + }, +#endif /* CONFIG_GK20A_CTXSW_TRACE */ .zbc = { .add_color = gp10b_gr_zbc_add_color, .add_depth = gp10b_gr_zbc_add_depth, @@ -802,29 +825,6 @@ static const struct gpu_ops gv11b_ops = { .get_netlist_name = gv11b_netlist_get_name, .is_fw_defined = gv11b_netlist_is_firmware_defined, }, -#ifdef CONFIG_GK20A_CTXSW_TRACE - .fecs_trace = { - .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc, - .free_user_buffer = gk20a_ctxsw_dev_ring_free, - .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer, - .init = nvgpu_gr_fecs_trace_init, - .deinit = nvgpu_gr_fecs_trace_deinit, - .enable = nvgpu_gr_fecs_trace_enable, - .disable = nvgpu_gr_fecs_trace_disable, - .is_enabled = nvgpu_gr_fecs_trace_is_enabled, - .reset = nvgpu_gr_fecs_trace_reset, - .flush = NULL, - .poll = nvgpu_gr_fecs_trace_poll, - .bind_channel = nvgpu_gr_fecs_trace_bind_channel, - .unbind_channel = nvgpu_gr_fecs_trace_unbind_channel, - .max_entries = nvgpu_gr_fecs_trace_max_entries, - .get_buffer_full_mailbox_val = - gv11b_fecs_trace_get_buffer_full_mailbox_val, - .get_read_index = gm20b_fecs_trace_get_read_index, - .get_write_index = gm20b_fecs_trace_get_write_index, - .set_read_index = gm20b_fecs_trace_set_read_index, - }, -#endif /* CONFIG_GK20A_CTXSW_TRACE */ .mm = { .gmmu_map = gk20a_locked_gmmu_map, .gmmu_unmap = gk20a_locked_gmmu_unmap, @@ -1119,9 +1119,6 @@ int gv11b_init_hal(struct gk20a *g) gops->pbdma_status = gv11b_ops.pbdma_status; gops->netlist = gv11b_ops.netlist; gops->mm = gv11b_ops.mm; -#ifdef CONFIG_GK20A_CTXSW_TRACE - gops->fecs_trace = gv11b_ops.fecs_trace; -#endif gops->therm = gv11b_ops.therm; gops->pmu = gv11b_ops.pmu; gops->regops = gv11b_ops.regops; diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 9a21c8e0c..0ba2b693e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -609,6 +609,42 @@ struct gpu_ops { u32 (*get_pd_dist_skip_table_size)(void); } config; +#ifdef CONFIG_GK20A_CTXSW_TRACE + struct { + int (*init)(struct gk20a *g); + int (*max_entries)(struct gk20a *, + struct nvgpu_gpu_ctxsw_trace_filter *filter); + int (*flush)(struct gk20a *g); + int (*poll)(struct gk20a *g); + int (*enable)(struct gk20a *g); + int (*disable)(struct gk20a *g); + bool (*is_enabled)(struct gk20a *g); + int (*reset)(struct gk20a *g); + int (*bind_channel)(struct gk20a *g, + struct nvgpu_mem *inst_block, + struct nvgpu_gr_subctx *subctx, + struct nvgpu_gr_ctx *gr_ctx, pid_t pid, u32 vmid); + int (*unbind_channel)(struct gk20a *g, + struct nvgpu_mem *inst_block); + int (*deinit)(struct gk20a *g); + int (*alloc_user_buffer)(struct gk20a *g, + void **buf, size_t *size); + int (*free_user_buffer)(struct gk20a *g); + int (*mmap_user_buffer)(struct gk20a *g, + struct vm_area_struct *vma); + int (*set_filter)(struct gk20a *g, + struct nvgpu_gpu_ctxsw_trace_filter *filter); + u32 (*get_buffer_full_mailbox_val)(void); + int (*get_read_index)(struct gk20a *g); + int (*get_write_index)(struct gk20a *g); + int (*set_read_index)(struct gk20a *g, int index); + void (*vm_dev_write)(struct gk20a *g, u8 vmid, + u32 *vm_update_mask, + struct nvgpu_gpu_ctxsw_trace_entry *entry); + void (*vm_dev_update)(struct gk20a *g, u32 vm_update_mask); + } fecs_trace; +#endif + struct { int (*add_color)(struct gk20a *g, struct nvgpu_gr_zbc_entry *color_val, @@ -1092,46 +1128,6 @@ struct gpu_ops { int (*get_netlist_name)(struct gk20a *g, int index, char *name); bool (*is_fw_defined)(void); } netlist; -#ifdef CONFIG_GK20A_CTXSW_TRACE - /* - * Currently only supported on Linux due to the extremely tight - * integration with Linux device driver structure (in particular - * mmap). - */ - struct { - int (*init)(struct gk20a *g); - int (*max_entries)(struct gk20a *, - struct nvgpu_gpu_ctxsw_trace_filter *filter); - int (*flush)(struct gk20a *g); - int (*poll)(struct gk20a *g); - int (*enable)(struct gk20a *g); - int (*disable)(struct gk20a *g); - bool (*is_enabled)(struct gk20a *g); - int (*reset)(struct gk20a *g); - int (*bind_channel)(struct gk20a *g, - struct nvgpu_mem *inst_block, - struct nvgpu_gr_subctx *subctx, - struct nvgpu_gr_ctx *gr_ctx, pid_t pid, u32 vmid); - int (*unbind_channel)(struct gk20a *g, - struct nvgpu_mem *inst_block); - int (*deinit)(struct gk20a *g); - int (*alloc_user_buffer)(struct gk20a *g, - void **buf, size_t *size); - int (*free_user_buffer)(struct gk20a *g); - int (*mmap_user_buffer)(struct gk20a *g, - struct vm_area_struct *vma); - int (*set_filter)(struct gk20a *g, - struct nvgpu_gpu_ctxsw_trace_filter *filter); - u32 (*get_buffer_full_mailbox_val)(void); - int (*get_read_index)(struct gk20a *g); - int (*get_write_index)(struct gk20a *g); - int (*set_read_index)(struct gk20a *g, int index); - void (*vm_dev_write)(struct gk20a *g, u8 vmid, - u32 *vm_update_mask, - struct nvgpu_gpu_ctxsw_trace_entry *entry); - void (*vm_dev_update)(struct gk20a *g, u32 vm_update_mask); - } fecs_trace; -#endif struct { u64 (*gmmu_map)(struct vm_gk20a *vm, u64 map_offset, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/fecs_trace.h b/drivers/gpu/nvgpu/include/nvgpu/gr/fecs_trace.h index 0df5834be..37a80301a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/fecs_trace.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/fecs_trace.h @@ -174,13 +174,13 @@ int nvgpu_gr_fecs_trace_unbind_channel(struct gk20a *g, * Below functions are defined in OS-specific code. * Declare them here in common header since they are called from common code */ -int gk20a_ctxsw_dev_ring_alloc(struct gk20a *g, void **buf, size_t *size); -int gk20a_ctxsw_dev_ring_free(struct gk20a *g); -int gk20a_ctxsw_dev_mmap_buffer(struct gk20a *g, struct vm_area_struct *vma); -void gk20a_ctxsw_trace_tsg_reset(struct gk20a *g, struct tsg_gk20a *tsg); +int nvgpu_gr_fecs_trace_ring_alloc(struct gk20a *g, void **buf, size_t *size); +int nvgpu_gr_fecs_trace_ring_free(struct gk20a *g); +int nvgpu_gr_fecs_trace_mmap_buffer(struct gk20a *g, struct vm_area_struct *vma); +void nvgpu_gr_fecs_trace_add_tsg_reset(struct gk20a *g, struct tsg_gk20a *tsg); u8 nvgpu_gpu_ctxsw_tags_to_common_tags(u8 tags); -int gk20a_ctxsw_trace_write(struct gk20a *g, +int nvgpu_gr_fecs_trace_write_entry(struct gk20a *g, struct nvgpu_gpu_ctxsw_trace_entry *entry); -void gk20a_ctxsw_trace_wake_up(struct gk20a *g, int vmid); +void nvgpu_gr_fecs_trace_wake_up(struct gk20a *g, int vmid); #endif /* NVGPU_GR_FECS_TRACE_H */ diff --git a/drivers/gpu/nvgpu/os/linux/debug_fecs_trace.c b/drivers/gpu/nvgpu/os/linux/debug_fecs_trace.c index 521123f98..05e1da9de 100644 --- a/drivers/gpu/nvgpu/os/linux/debug_fecs_trace.c +++ b/drivers/gpu/nvgpu/os/linux/debug_fecs_trace.c @@ -132,7 +132,7 @@ static int gk20a_fecs_trace_debugfs_read(void *arg, u64 *val) return err; } - *val = g->ops.fecs_trace.get_read_index(g); + *val = g->ops.gr.fecs_trace.get_read_index(g); gk20a_idle(g); return 0; @@ -148,7 +148,7 @@ static int gk20a_fecs_trace_debugfs_write(void *arg, u64 *val) return err; } - *val = g->ops.fecs_trace.get_write_index(g); + *val = g->ops.gr.fecs_trace.get_write_index(g); gk20a_idle(g); return 0; diff --git a/drivers/gpu/nvgpu/os/linux/fecs_trace_linux.c b/drivers/gpu/nvgpu/os/linux/fecs_trace_linux.c index ba787a0b7..ad83c540e 100644 --- a/drivers/gpu/nvgpu/os/linux/fecs_trace_linux.c +++ b/drivers/gpu/nvgpu/os/linux/fecs_trace_linux.c @@ -153,7 +153,7 @@ static int gk20a_ctxsw_dev_ioctl_trace_enable(struct gk20a_ctxsw_dev *dev) nvgpu_mutex_acquire(&dev->write_lock); dev->write_enabled = true; nvgpu_mutex_release(&dev->write_lock); - dev->g->ops.fecs_trace.enable(dev->g); + dev->g->ops.gr.fecs_trace.enable(dev->g); return 0; } @@ -162,7 +162,7 @@ static int gk20a_ctxsw_dev_ioctl_trace_disable(struct gk20a_ctxsw_dev *dev) struct gk20a *g = dev->g; nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, "trace disabled"); - dev->g->ops.fecs_trace.disable(dev->g); + dev->g->ops.gr.fecs_trace.disable(dev->g); nvgpu_mutex_acquire(&dev->write_lock); dev->write_enabled = false; nvgpu_mutex_release(&dev->write_lock); @@ -180,11 +180,11 @@ static int gk20a_ctxsw_dev_alloc_buffer(struct gk20a_ctxsw_dev *dev, return -EBUSY; if (dev->hdr) { - g->ops.fecs_trace.free_user_buffer(g); + g->ops.gr.fecs_trace.free_user_buffer(g); dev->hdr = NULL; } - err = g->ops.fecs_trace.alloc_user_buffer(g, &buf, size); + err = g->ops.gr.fecs_trace.alloc_user_buffer(g, &buf, size); if (err) return err; @@ -199,7 +199,7 @@ static int gk20a_ctxsw_dev_alloc_buffer(struct gk20a_ctxsw_dev *dev, return 0; } -int gk20a_ctxsw_dev_ring_alloc(struct gk20a *g, +int nvgpu_gr_fecs_trace_ring_alloc(struct gk20a *g, void **buf, size_t *size) { struct nvgpu_ctxsw_ring_header *hdr; @@ -223,7 +223,7 @@ int gk20a_ctxsw_dev_ring_alloc(struct gk20a *g, return 0; } -int gk20a_ctxsw_dev_ring_free(struct gk20a *g) +int nvgpu_gr_fecs_trace_ring_free(struct gk20a *g) { struct gk20a_ctxsw_dev *dev = &g->ctxsw_trace->devs[0]; @@ -276,8 +276,8 @@ static int gk20a_ctxsw_dev_ioctl_set_filter(struct gk20a_ctxsw_dev *dev, nvgpu_set_ctxsw_trace_filter_args(&dev->filter, &args->filter); nvgpu_mutex_release(&dev->write_lock); - if (g->ops.fecs_trace.set_filter) - g->ops.fecs_trace.set_filter(g, &dev->filter); + if (g->ops.gr.fecs_trace.set_filter) + g->ops.gr.fecs_trace.set_filter(g, &dev->filter); return 0; } @@ -302,11 +302,11 @@ static int gk20a_ctxsw_dev_ioctl_poll(struct gk20a_ctxsw_dev *dev) if (err) return err; - if (g->ops.fecs_trace.flush) - err = g->ops.fecs_trace.flush(g); + if (g->ops.gr.fecs_trace.flush) + err = g->ops.gr.fecs_trace.flush(g); if (likely(!err)) - err = g->ops.fecs_trace.poll(g); + err = g->ops.gr.fecs_trace.poll(g); gk20a_idle(g); return err; @@ -362,7 +362,7 @@ int gk20a_ctxsw_dev_open(struct inode *inode, struct file *filp) NVGPU_CTXSW_FILTER_SET_ALL(&dev->filter); /* compute max number of entries generated with this filter */ - n = g->ops.fecs_trace.max_entries(g, &dev->filter); + n = g->ops.gr.fecs_trace.max_entries(g, &dev->filter); size = sizeof(struct nvgpu_ctxsw_ring_header) + n * sizeof(struct nvgpu_gpu_ctxsw_trace_entry); @@ -397,12 +397,12 @@ int gk20a_ctxsw_dev_release(struct inode *inode, struct file *filp) nvgpu_mutex_acquire(&dev->write_lock); if (dev->write_enabled) { dev->write_enabled = false; - g->ops.fecs_trace.disable(g); + g->ops.gr.fecs_trace.disable(g); } nvgpu_mutex_release(&dev->write_lock); if (dev->hdr) { - dev->g->ops.fecs_trace.free_user_buffer(dev->g); + dev->g->ops.gr.fecs_trace.free_user_buffer(dev->g); dev->hdr = NULL; } gk20a_put(g); @@ -508,7 +508,7 @@ static struct vm_operations_struct gk20a_ctxsw_dev_vma_ops = { .close = gk20a_ctxsw_dev_vma_close, }; -int gk20a_ctxsw_dev_mmap_buffer(struct gk20a *g, +int nvgpu_gr_fecs_trace_mmap_buffer(struct gk20a *g, struct vm_area_struct *vma) { return remap_vmalloc_range(vma, g->ctxsw_trace->devs[0].hdr, 0); @@ -523,7 +523,7 @@ int gk20a_ctxsw_dev_mmap(struct file *filp, struct vm_area_struct *vma) nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, "vm_start=%lx vm_end=%lx", vma->vm_start, vma->vm_end); - ret = dev->g->ops.fecs_trace.mmap_user_buffer(dev->g, vma); + ret = dev->g->ops.gr.fecs_trace.mmap_user_buffer(dev->g, vma); if (likely(!ret)) { vma->vm_private_data = dev; vma->vm_ops = &gk20a_ctxsw_dev_vma_ops; @@ -565,7 +565,7 @@ int gk20a_ctxsw_trace_init(struct gk20a *g) nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, "g=%p trace=%p", g, trace); /* if tracing is not supported, skip this */ - if (!g->ops.fecs_trace.init) + if (!g->ops.gr.fecs_trace.init) return 0; if (likely(trace)) @@ -580,7 +580,7 @@ int gk20a_ctxsw_trace_init(struct gk20a *g) if (err) goto fail; - err = g->ops.fecs_trace.init(g); + err = g->ops.gr.fecs_trace.init(g); if (unlikely(err)) goto fail; @@ -589,7 +589,7 @@ int gk20a_ctxsw_trace_init(struct gk20a *g) return 0; fail: - (void) memset(&g->ops.fecs_trace, 0, sizeof(g->ops.fecs_trace)); + (void) memset(&g->ops.gr.fecs_trace, 0, sizeof(g->ops.gr.fecs_trace)); nvgpu_kfree(g, trace); g->ctxsw_trace = NULL; return err; @@ -619,11 +619,11 @@ void gk20a_ctxsw_trace_cleanup(struct gk20a *g) nvgpu_kfree(g, g->ctxsw_trace); g->ctxsw_trace = NULL; - g->ops.fecs_trace.deinit(g); + g->ops.gr.fecs_trace.deinit(g); #endif } -int gk20a_ctxsw_trace_write(struct gk20a *g, +int nvgpu_gr_fecs_trace_write_entry(struct gk20a *g, struct nvgpu_gpu_ctxsw_trace_entry *entry) { struct nvgpu_ctxsw_ring_header *hdr; @@ -702,7 +702,7 @@ int gk20a_ctxsw_trace_write(struct gk20a *g, return ret; disable: - g->ops.fecs_trace.disable(g); + g->ops.gr.fecs_trace.disable(g); drop: hdr->drop_count++; @@ -719,7 +719,7 @@ done: return ret; } -void gk20a_ctxsw_trace_wake_up(struct gk20a *g, int vmid) +void nvgpu_gr_fecs_trace_wake_up(struct gk20a *g, int vmid) { struct gk20a_ctxsw_dev *dev; @@ -730,7 +730,7 @@ void gk20a_ctxsw_trace_wake_up(struct gk20a *g, int vmid) nvgpu_cond_signal_interruptible(&dev->readout_wq); } -void gk20a_ctxsw_trace_tsg_reset(struct gk20a *g, struct tsg_gk20a *tsg) +void nvgpu_gr_fecs_trace_add_tsg_reset(struct gk20a *g, struct tsg_gk20a *tsg) { #ifdef CONFIG_GK20A_CTXSW_TRACE struct nvgpu_gpu_ctxsw_trace_entry entry = { @@ -744,8 +744,8 @@ void gk20a_ctxsw_trace_tsg_reset(struct gk20a *g, struct tsg_gk20a *tsg) return; g->ops.ptimer.read_ptimer(g, &entry.timestamp); - gk20a_ctxsw_trace_write(g, &entry); - gk20a_ctxsw_trace_wake_up(g, 0); + nvgpu_gr_fecs_trace_write_entry(g, &entry); + nvgpu_gr_fecs_trace_wake_up(g, 0); #endif trace_gk20a_channel_reset(~0, tsg->tsgid); } diff --git a/drivers/gpu/nvgpu/os/linux/vgpu/fecs_trace_vgpu_linux.c b/drivers/gpu/nvgpu/os/linux/vgpu/fecs_trace_vgpu_linux.c index bc85a7ca5..eb6c1f2c8 100644 --- a/drivers/gpu/nvgpu/os/linux/vgpu/fecs_trace_vgpu_linux.c +++ b/drivers/gpu/nvgpu/os/linux/vgpu/fecs_trace_vgpu_linux.c @@ -25,7 +25,7 @@ void vgpu_fecs_trace_data_update(struct gk20a *g) { - gk20a_ctxsw_trace_wake_up(g, 0); + nvgpu_gr_fecs_trace_wake_up(g, 0); } int vgpu_alloc_user_buffer(struct gk20a *g, void **buf, size_t *size) diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 6f9d8a8e1..7637f2c06 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -615,6 +615,29 @@ static const struct gpu_ops tu104_ops = { .get_pd_dist_skip_table_size = gm20b_gr_config_get_pd_dist_skip_table_size, }, +#ifdef CONFIG_GK20A_CTXSW_TRACE + .fecs_trace = { + .alloc_user_buffer = nvgpu_gr_fecs_trace_ring_alloc, + .free_user_buffer = nvgpu_gr_fecs_trace_ring_free, + .mmap_user_buffer = nvgpu_gr_fecs_trace_mmap_buffer, + .init = nvgpu_gr_fecs_trace_init, + .deinit = nvgpu_gr_fecs_trace_deinit, + .enable = nvgpu_gr_fecs_trace_enable, + .disable = nvgpu_gr_fecs_trace_disable, + .is_enabled = nvgpu_gr_fecs_trace_is_enabled, + .reset = nvgpu_gr_fecs_trace_reset, + .flush = NULL, + .poll = nvgpu_gr_fecs_trace_poll, + .bind_channel = nvgpu_gr_fecs_trace_bind_channel, + .unbind_channel = nvgpu_gr_fecs_trace_unbind_channel, + .max_entries = nvgpu_gr_fecs_trace_max_entries, + .get_buffer_full_mailbox_val = + gv11b_fecs_trace_get_buffer_full_mailbox_val, + .get_read_index = gm20b_fecs_trace_get_read_index, + .get_write_index = gm20b_fecs_trace_get_write_index, + .set_read_index = gm20b_fecs_trace_set_read_index, + }, +#endif /* CONFIG_GK20A_CTXSW_TRACE */ .zbc = { .add_color = gp10b_gr_zbc_add_color, .add_depth = gp10b_gr_zbc_add_depth, @@ -877,29 +900,6 @@ static const struct gpu_ops tu104_ops = { .get_netlist_name = tu104_netlist_get_name, .is_fw_defined = tu104_netlist_is_firmware_defined, }, -#ifdef CONFIG_GK20A_CTXSW_TRACE - .fecs_trace = { - .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc, - .free_user_buffer = gk20a_ctxsw_dev_ring_free, - .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer, - .init = nvgpu_gr_fecs_trace_init, - .deinit = nvgpu_gr_fecs_trace_deinit, - .enable = nvgpu_gr_fecs_trace_enable, - .disable = nvgpu_gr_fecs_trace_disable, - .is_enabled = nvgpu_gr_fecs_trace_is_enabled, - .reset = nvgpu_gr_fecs_trace_reset, - .flush = NULL, - .poll = nvgpu_gr_fecs_trace_poll, - .bind_channel = nvgpu_gr_fecs_trace_bind_channel, - .unbind_channel = nvgpu_gr_fecs_trace_unbind_channel, - .max_entries = nvgpu_gr_fecs_trace_max_entries, - .get_buffer_full_mailbox_val = - gv11b_fecs_trace_get_buffer_full_mailbox_val, - .get_read_index = gm20b_fecs_trace_get_read_index, - .get_write_index = gm20b_fecs_trace_get_write_index, - .set_read_index = gm20b_fecs_trace_set_read_index, - }, -#endif /* CONFIG_GK20A_CTXSW_TRACE */ .mm = { .gmmu_map = gk20a_locked_gmmu_map, .gmmu_unmap = gk20a_locked_gmmu_unmap, @@ -1283,9 +1283,6 @@ int tu104_init_hal(struct gk20a *g) gops->pbdma_status = tu104_ops.pbdma_status; gops->netlist = tu104_ops.netlist; gops->mm = tu104_ops.mm; -#ifdef CONFIG_GK20A_CTXSW_TRACE - gops->fecs_trace = tu104_ops.fecs_trace; -#endif gops->pramin = tu104_ops.pramin; gops->therm = tu104_ops.therm; gops->pmu = tu104_ops.pmu;