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gpu: nvgpu: add MAP_ACCESS_TYPE enabled flag

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On Linux, nvgpu mapping ioctl provides option to specify the access
type flags for the mapping. This support is not implemented for
other OS. For nvrm_gpu to know when to set these flags add new
enabled flag *_MAP_ACCESS_TYPE that is enabled only for Linux.

Bug 200621157

Change-Id: If1397bb0d5fdc5589458d92f24647afa586af1c2
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2363829
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sagar Kamble
2020-06-18 18:33:15 +05:30
committed by Alex Waterman
parent 8156a23a6e
commit 7fea56cf97
4 changed files with 10 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/include/nvgpu/enabled.h
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@@ -261,10 +261,13 @@ struct gk20a;
/** PLC Compression */ /** PLC Compression */
#define NVGPU_SUPPORT_POST_L2_COMPRESSION 89U #define NVGPU_SUPPORT_POST_L2_COMPRESSION 89U
/** GMMU map access type support */
#define NVGPU_SUPPORT_MAP_ACCESS_TYPE 90U
/* /*
* Must be greater than the largest bit offset in the above list. * Must be greater than the largest bit offset in the above list.
*/ */
#define NVGPU_MAX_ENABLED_BITS 90U #define NVGPU_MAX_ENABLED_BITS 91U
/** /**
* @brief Check if the passed flag is enabled. * @brief Check if the passed flag is enabled.

4
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
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@@ -256,7 +256,9 @@ static struct nvgpu_flags_mapping flags_mapping[] = {
{NVGPU_GPU_FLAGS_SUPPORT_SM_TTU, {NVGPU_GPU_FLAGS_SUPPORT_SM_TTU,
NVGPU_SUPPORT_SM_TTU}, NVGPU_SUPPORT_SM_TTU},
{NVGPU_GPU_FLAGS_SUPPORT_POST_L2_COMPRESSION, {NVGPU_GPU_FLAGS_SUPPORT_POST_L2_COMPRESSION,
NVGPU_SUPPORT_POST_L2_COMPRESSION} NVGPU_SUPPORT_POST_L2_COMPRESSION},
{NVGPU_GPU_FLAGS_SUPPORT_MAP_ACCESS_TYPE,
NVGPU_SUPPORT_MAP_ACCESS_TYPE}
}; };
static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g) static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g)

1
drivers/gpu/nvgpu/os/linux/module.c
View File

@@ -317,6 +317,7 @@ void gk20a_init_linux_characteristics(struct gk20a *g)
nvgpu_set_enabled(g, NVGPU_SUPPORT_PARTIAL_MAPPINGS, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_PARTIAL_MAPPINGS, true);
nvgpu_set_enabled(g, NVGPU_SUPPORT_DETERMINISTIC_OPTS, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_DETERMINISTIC_OPTS, true);
nvgpu_set_enabled(g, NVGPU_SUPPORT_USERSPACE_MANAGED_AS, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_USERSPACE_MANAGED_AS, true);
nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_ACCESS_TYPE, true);
if (!IS_ENABLED(CONFIG_NVGPU_SYNCFD_NONE)) { if (!IS_ENABLED(CONFIG_NVGPU_SYNCFD_NONE)) {
nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNC_FENCE_FDS, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNC_FENCE_FDS, true);

2
include/uapi/linux/nvgpu.h
View File

@@ -179,6 +179,8 @@ struct nvgpu_gpu_zbc_query_table_args {
#define NVGPU_GPU_FLAGS_SUPPORT_SM_TTU (1ULL << 37) #define NVGPU_GPU_FLAGS_SUPPORT_SM_TTU (1ULL << 37)
/* Compression PLC is enabled */ /* Compression PLC is enabled */
#define NVGPU_GPU_FLAGS_SUPPORT_POST_L2_COMPRESSION (1ULL << 38) #define NVGPU_GPU_FLAGS_SUPPORT_POST_L2_COMPRESSION (1ULL << 38)
/** GMMU map access type available */
#define NVGPU_GPU_FLAGS_SUPPORT_MAP_ACCESS_TYPE (1ULL << 39)
/* SM LRF ECC is enabled */ /* SM LRF ECC is enabled */
#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60) #define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60)
/* SM SHM ECC is enabled */ /* SM SHM ECC is enabled */