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gpu: nvgpu: add MAP_ACCESS_TYPE enabled flag
On Linux, nvgpu mapping ioctl provides option to specify the access type flags for the mapping. This support is not implemented for other OS. For nvrm_gpu to know when to set these flags add new enabled flag *_MAP_ACCESS_TYPE that is enabled only for Linux. Bug 200621157 Change-Id: If1397bb0d5fdc5589458d92f24647afa586af1c2 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2363829 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
This commit is contained in:
committed by
Alex Waterman
parent
8156a23a6e
commit
7fea56cf97
@@ -261,10 +261,13 @@ struct gk20a;
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/** PLC Compression */
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#define NVGPU_SUPPORT_POST_L2_COMPRESSION 89U
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/** GMMU map access type support */
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#define NVGPU_SUPPORT_MAP_ACCESS_TYPE 90U
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/*
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* Must be greater than the largest bit offset in the above list.
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*/
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#define NVGPU_MAX_ENABLED_BITS 90U
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#define NVGPU_MAX_ENABLED_BITS 91U
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/**
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* @brief Check if the passed flag is enabled.
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@@ -256,7 +256,9 @@ static struct nvgpu_flags_mapping flags_mapping[] = {
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{NVGPU_GPU_FLAGS_SUPPORT_SM_TTU,
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NVGPU_SUPPORT_SM_TTU},
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{NVGPU_GPU_FLAGS_SUPPORT_POST_L2_COMPRESSION,
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NVGPU_SUPPORT_POST_L2_COMPRESSION}
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NVGPU_SUPPORT_POST_L2_COMPRESSION},
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{NVGPU_GPU_FLAGS_SUPPORT_MAP_ACCESS_TYPE,
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NVGPU_SUPPORT_MAP_ACCESS_TYPE}
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};
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static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g)
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@@ -317,6 +317,7 @@ void gk20a_init_linux_characteristics(struct gk20a *g)
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nvgpu_set_enabled(g, NVGPU_SUPPORT_PARTIAL_MAPPINGS, true);
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nvgpu_set_enabled(g, NVGPU_SUPPORT_DETERMINISTIC_OPTS, true);
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nvgpu_set_enabled(g, NVGPU_SUPPORT_USERSPACE_MANAGED_AS, true);
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nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_ACCESS_TYPE, true);
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if (!IS_ENABLED(CONFIG_NVGPU_SYNCFD_NONE)) {
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nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNC_FENCE_FDS, true);
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@@ -179,6 +179,8 @@ struct nvgpu_gpu_zbc_query_table_args {
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#define NVGPU_GPU_FLAGS_SUPPORT_SM_TTU (1ULL << 37)
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/* Compression PLC is enabled */
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#define NVGPU_GPU_FLAGS_SUPPORT_POST_L2_COMPRESSION (1ULL << 38)
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/** GMMU map access type available */
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#define NVGPU_GPU_FLAGS_SUPPORT_MAP_ACCESS_TYPE (1ULL << 39)
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/* SM LRF ECC is enabled */
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#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60)
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/* SM SHM ECC is enabled */
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