From 7ff3d7d11c0be8f28c9a7bec9e60fa4015d83a2e Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Tue, 30 Apr 2019 10:48:11 -0700 Subject: [PATCH] gpu: nvgpu: runlist MISRA fix for rule 13.5 MISRA Rule 13.5 mandates that the right hand operand of a logical && or || operator does not contain persistent side effects. Removed use of nvgpu_readl from the if condition. Jira NVGPU-3378 Change-Id: Ia5d7c083d6827f8a7db152757e683a4a06418b21 Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/2109477 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.c b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.c index bf8cb9b6f..3d2be3f9c 100644 --- a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.c +++ b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.c @@ -157,9 +157,12 @@ int gk20a_fifo_reschedule_preempt_next(struct channel_gk20a *ch, return ret; } - if (wait_preempt && ((nvgpu_readl(g, fifo_preempt_r()) & - fifo_preempt_pending_true_f()) != 0U)) { - return ret; + if (wait_preempt) { + u32 val = nvgpu_readl(g, fifo_preempt_r()); + + if ((val & fifo_preempt_pending_true_f()) != 0U) { + return ret; + } } fecsstat0 = g->ops.gr.falcon.read_fecs_ctxsw_mailbox(g,