From 8009a4f8c8677d290cf8fc4d1b8ab6680a338fc5 Mon Sep 17 00:00:00 2001 From: Rajesh Devaraj Date: Wed, 21 Aug 2019 21:20:14 +0530 Subject: [PATCH] gpu: nvgpu: check slice and tpc id This patch adds the check to validate the slice id and tpc id before packing them along with ltc id and gpc id, respectively. JIRA NVGPU-3867 Change-Id: I01cf095327ecc9c567c2d074ef1daa944377d15f Signed-off-by: Rajesh Devaraj Reviewed-on: https://git-master.nvidia.com/r/2180374 Reviewed-by: Raghuram Kothakota GVS: Gerrit_Virtual_Submit Reviewed-by: Ankur Kishore Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c | 28 +++++++++++++++++++ .../nvgpu/hal/ltc/intr/ltc_intr_gv11b_fusa.c | 6 ++++ 2 files changed, 34 insertions(+) diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c index 9678b7c4f..07298d159 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c @@ -900,6 +900,10 @@ void gv11b_gr_intr_set_hww_esr_report_mask(struct gk20a *g) static void gv11b_gr_intr_report_l1_tag_uncorrected_err(struct gk20a *g, u32 l1_tag_ecc_status, u32 gpc, u32 tpc) { + if (tpc > 255U) { + nvgpu_log(g, gpu_dbg_intr, "Invalid tpc id=%d", tpc); + tpc = tpc & 0xFFU; + } if ((l1_tag_ecc_status & (gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m() | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_1_m())) != 0U) { @@ -927,6 +931,10 @@ static void gv11b_gr_intr_report_l1_tag_uncorrected_err(struct gk20a *g, static void gv11b_gr_intr_report_l1_tag_corrected_err(struct gk20a *g, u32 l1_tag_ecc_status, u32 gpc, u32 tpc) { + if (tpc > 255U) { + nvgpu_log(g, gpu_dbg_intr, "Invalid tpc id=%d", tpc); + tpc = tpc & 0xFFU; + } if ((l1_tag_ecc_status & (gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m() | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_1_m())) != 0U) { @@ -1110,6 +1118,10 @@ static void gv11b_gr_intr_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc is_lrf_ecc_uncorrected_total_err_overflow = gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(lrf_ecc_status) != 0U; + if (tpc > 255U) { + nvgpu_log(g, gpu_dbg_intr, "Invalid tpc id=%d", tpc); + tpc = tpc & 0xFFU; + } if ((lrf_corrected_err_count_delta > 0U) || is_lrf_ecc_corrected_total_err_overflow) { nvgpu_log(g, gpu_dbg_fn | gpu_dbg_intr, "corrected error (SBE) detected in SM LRF! err_mask [%08x] is_overf [%d]", @@ -1215,6 +1227,10 @@ static void gv11b_gr_intr_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc is_cbu_ecc_uncorrected_total_err_overflow = gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(cbu_ecc_status) != 0U; + if (tpc > 255U) { + nvgpu_log(g, gpu_dbg_intr, "Invalid tpc id=%d", tpc); + tpc = tpc & 0xFFU; + } if ((cbu_corrected_err_count_delta > 0U) || is_cbu_ecc_corrected_total_err_overflow) { nvgpu_log(g, gpu_dbg_fn | gpu_dbg_intr, "corrected error (SBE) detected in SM CBU! err_mask [%08x] is_overf [%d]", @@ -1314,6 +1330,10 @@ static void gv11b_gr_intr_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 is_l1_data_ecc_uncorrected_total_err_overflow = gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(l1_data_ecc_status) != 0U; + if (tpc > 255U) { + nvgpu_log(g, gpu_dbg_intr, "Invalid tpc id=%d", tpc); + tpc = tpc & 0xFFU; + } if ((l1_data_corrected_err_count_delta > 0U) || is_l1_data_ecc_corrected_total_err_overflow) { nvgpu_log(g, gpu_dbg_fn | gpu_dbg_intr, "corrected error (SBE) detected in SM L1 data! err_mask [%08x] is_overf [%d]", @@ -1369,6 +1389,10 @@ static void gv11b_gr_intr_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 static void gv11b_gr_intr_report_icache_uncorrected_err(struct gk20a *g, u32 icache_ecc_status, u32 gpc, u32 tpc) { + if (tpc > 255U) { + nvgpu_log(g, gpu_dbg_intr, "Invalid tpc id=%d", tpc); + tpc = tpc & 0xFFU; + } if ((icache_ecc_status & gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_data_m()) != 0U) { (void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM, @@ -1402,6 +1426,10 @@ static void gv11b_gr_intr_report_icache_uncorrected_err(struct gk20a *g, static void gv11b_gr_intr_report_icache_corrected_err(struct gk20a *g, u32 icache_ecc_status, u32 gpc, u32 tpc) { + if (tpc > 255U) { + nvgpu_log(g, gpu_dbg_intr, "Invalid tpc id=%d", tpc); + tpc = tpc & 0xFFU; + } if ((icache_ecc_status & gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_data_m()) != 0U) { (void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM, diff --git a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b_fusa.c index 91fff2b22..e0fe15b83 100644 --- a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b_fusa.c @@ -166,6 +166,12 @@ static void gv11b_ltc_intr_handle_lts_interrupts(struct gk20a *g, "ltc:%d lts: %d cache ecc interrupt intr: 0x%x", ltc, slice, ltc_intr3); + if (slice > 255U) { + nvgpu_log(g, gpu_dbg_intr, "Invalid slice id=%d", + slice); + slice = slice & 0xFFU; + } + if ((ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m()) != 0U) { (void) nvgpu_report_ecc_err(g,