diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c b/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c
index 8c7cc40d3..34ee0bef1 100644
--- a/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c
@@ -42,6 +42,7 @@
 void gm20b_ltc_init_fs_state(struct gk20a *g)
 {
 	u32 reg;
+	u32 line_size = 512U;
 
 	nvgpu_log_info(g, "initialize gm20b l2");
 
@@ -53,7 +54,7 @@ void gm20b_ltc_init_fs_state(struct gk20a *g)
 	reg = gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r());
 	g->ltc->slices_per_ltc = ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(reg);
 	g->ltc->cacheline_size =
-		U32(512) << ltc_ltcs_ltss_cbc_param_cache_line_size_v(reg);
+		line_size << ltc_ltcs_ltss_cbc_param_cache_line_size_v(reg);
 
 	gk20a_writel(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r(),
 	g->ltc->ltc_count);
@@ -116,8 +117,8 @@ void gm20b_flush_ltc(struct gk20a *g)
 		}
 
 		do {
-			int cmgmt1 = ltc_ltc0_ltss_tstg_cmgmt1_r() +
-				     ltc * ltc_stride;
+			u32 cmgmt1 = (u32)(ltc_ltc0_ltss_tstg_cmgmt1_r() +
+							(ltc * ltc_stride));
 			op_pending = gk20a_readl(g, cmgmt1);
 			is_clean_pending_set = (op_pending &
 				ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f()) != 0U;
@@ -148,8 +149,8 @@ void gm20b_flush_ltc(struct gk20a *g)
 		}
 
 		do {
-			int cmgmt0 = ltc_ltc0_ltss_tstg_cmgmt0_r() +
-				     ltc * ltc_stride;
+			u32 cmgmt0 = (u32)(ltc_ltc0_ltss_tstg_cmgmt0_r() +
+							(ltc * ltc_stride));
 			op_pending = gk20a_readl(g, cmgmt0);
 			is_invalidate_pending_set = (op_pending &
 				ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f()) != 0U;
diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c b/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c
index 9cd9be78f..8a8cb5649 100644
--- a/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c
@@ -51,6 +51,7 @@ void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g,
 void gv11b_ltc_init_fs_state(struct gk20a *g)
 {
 	u32 reg;
+	u32 line_size = 512U;
 
 	nvgpu_log_info(g, "initialize gv11b l2");
 
@@ -62,7 +63,7 @@ void gv11b_ltc_init_fs_state(struct gk20a *g)
 	reg = gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r());
 	g->ltc->slices_per_ltc = ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(reg);;
 	g->ltc->cacheline_size =
-		U32(512) << ltc_ltcs_ltss_cbc_param_cache_line_size_v(reg);
+		line_size << ltc_ltcs_ltss_cbc_param_cache_line_size_v(reg);
 
 	g->ops.ltc.intr.configure(g);
 
diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_tu104.c b/drivers/gpu/nvgpu/hal/ltc/ltc_tu104.c
index 8465287a0..2e156887a 100644
--- a/drivers/gpu/nvgpu/hal/ltc/ltc_tu104.c
+++ b/drivers/gpu/nvgpu/hal/ltc/ltc_tu104.c
@@ -38,6 +38,7 @@
 void ltc_tu104_init_fs_state(struct gk20a *g)
 {
 	u32 reg;
+	u32 line_size = 512U;
 
 	gv11b_ltc_init_fs_state(g);
 
@@ -45,7 +46,7 @@ void ltc_tu104_init_fs_state(struct gk20a *g)
 	g->ltc->slices_per_ltc =
 		ltc_ltcs_ltss_cbc_param2_slices_per_ltc_v(reg);
 	g->ltc->cacheline_size =
-		U32(512) << ltc_ltcs_ltss_cbc_param2_cache_line_size_v(reg);
+		line_size << ltc_ltcs_ltss_cbc_param2_cache_line_size_v(reg);
 
 	/* disable PLC compression */
 	reg = nvgpu_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_1_r());