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gpu: nvgpu: Fix IPA to PA translation

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Background:
In Hypervisor mode dGPU device is configured in pass through mode for
the Guest (QNX/Linux). GMMU programming is handled by the guest which
converts a mapped buffer's GVA into SGLes in IPA (Intermediate/Guest
Physical address) which is then translated into PA (Acutual Physical
address) and programs the GMMU PTEes with correct GVA to PA mapping.
Incase of the vgpu this work is delegated to the RM server which takes care
of the GMMU programming and IPA to PA conversion.

Problem:
The current GMMU mapping logic in the guest assumes that PA range is
continuous over a given IPA range. Hence, it doesn't account for holes being
present in the PA range. But this is not the case, a continous IPA range
can be mapped to dis-contiguous PA ranges. In this situation the mapping
logic sets up GMMU PTEes ignoring the holes in physical memory and
creates GVA => PA mapping which intrudes into the PA ranges which are
reserved. This results in memory being corrupted.

This change takes into account holes being present in a given PA range and
for a  given IPA range it also identifies the discontiguous PA ranges and
sets up the PTE's appropriately.

Bug  200451447
Jira VQRM-5069

Change-Id: I354d984f6c44482e4576a173fce1e90ab52283ac
Signed-off-by: aalex <aalex@nvidia.com>
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1850972
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
aalex
2018-09-28 15:24:20 +05:30
committed by mobile promotions
parent 6c8be7cfe2
commit 80d03f34f7
8 changed files with 157 additions and 25 deletions
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9
drivers/gpu/nvgpu/os/linux/soc.c
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@@ -65,7 +65,7 @@ bool nvgpu_is_soc_t194_a01(struct gk20a *g)
* is enabled), the addresses we get from dma_alloc are IPAs. We need to
* convert them to PA.
*/
static u64 nvgpu_tegra_hv_ipa_pa(struct gk20a *g, u64 ipa)
static u64 nvgpu_tegra_hv_ipa_pa(struct gk20a *g, u64 ipa, u64 *pa_len)
{
struct device *dev = dev_from_gk20a(g);
struct gk20a_platform *platform = gk20a_get_platform(dev);
@@ -92,6 +92,13 @@ static u64 nvgpu_tegra_hv_ipa_pa(struct gk20a *g, u64 ipa)
}
} else {
pa = info.base + info.offset;
if (pa_len != NULL) {
/*
* Update the size of physical memory chunk after the
* specified offset.
*/
*pa_len = info.size - info.offset;
}
nvgpu_log(g, gpu_dbg_map_v,
"ipa=%llx vmid=%d -> pa=%llx "
"base=%llx offset=%llx size=%llx\n",