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gpu: nvgpu: add BVEC test for nvgpu_rc_pbdma_fault

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Update nvgpu_rc_pbdma_fault with invalid checks and add BVEC test
for it.

Make ga10b_fifo_pbdma_isr static.

NVGPU-6772

Change-Id: I5485760c53e1fff1278557a5b25659a1fc0e4eaf
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551617
(cherry picked from commit e917042d395d07cb902580bad3d5a7d0096cc303)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2623625
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2021-06-29 23:44:25 +05:30
committed by mobile promotions
parent d8e8eb65d3
commit 80efe558b1
24 changed files with 298 additions and 92 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/nvgpu/common/fifo/pbdma_status.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -42,6 +42,11 @@ bool nvgpu_pbdma_status_is_chsw_valid(struct nvgpu_pbdma_status_info
{
return pbdma_status->chsw_status == NVGPU_PBDMA_CHSW_STATUS_VALID;
}
bool nvgpu_pbdma_status_ch_not_loaded(struct nvgpu_pbdma_status_info
*pbdma_status)
{
return pbdma_status->chsw_status == NVGPU_PBDMA_CHSW_STATUS_INVALID;
}
bool nvgpu_pbdma_status_is_id_type_tsg(struct nvgpu_pbdma_status_info
*pbdma_status)
{

3
drivers/gpu/nvgpu/common/fifo/tsg.c
View File

@@ -621,9 +621,8 @@ void nvgpu_tsg_set_error_notifier(struct gk20a *g, struct nvgpu_tsg *tsg,
u32 error_notifier)
{
struct nvgpu_channel *ch = NULL;
u32 max_error_notifier_id = NVGPU_ERR_NOTIFIER_PBDMA_PUSHBUFFER_CRC_MISMATCH;
if (error_notifier > max_error_notifier_id) {
if (error_notifier >= NVGPU_ERR_NOTIFIER_INVAL) {
return;
}

36
drivers/gpu/nvgpu/common/rc/rc.c
View File

@@ -35,6 +35,7 @@
#include <nvgpu/error_notifier.h>
#include <nvgpu/pbdma_status.h>
#include <nvgpu/rc.h>
#include <nvgpu/nvgpu_init.h>
void nvgpu_rc_fifo_recover(struct gk20a *g, u32 eng_bitmask,
u32 hw_id, bool id_is_tsg,
@@ -94,11 +95,18 @@ void nvgpu_rc_ctxsw_timeout(struct gk20a *g, u32 eng_bitmask,
#endif
}
void nvgpu_rc_pbdma_fault(struct gk20a *g, u32 pbdma_id, u32 error_notifier,
int nvgpu_rc_pbdma_fault(struct gk20a *g, u32 pbdma_id, enum nvgpu_err_notif error_notifier,
struct nvgpu_pbdma_status_info *pbdma_status)
{
u32 id;
u32 id_type = PBDMA_STATUS_ID_TYPE_INVALID;
int err = 0;
u32 id;
if (error_notifier >= NVGPU_ERR_NOTIFIER_INVAL) {
nvgpu_err(g, "Invalid error notifier %u", error_notifier);
err = -EINVAL;
goto out;
}
nvgpu_log(g, gpu_dbg_info, "pbdma id %d error notifier %d",
pbdma_id, error_notifier);
@@ -111,10 +119,14 @@ void nvgpu_rc_pbdma_fault(struct gk20a *g, u32 pbdma_id, u32 error_notifier,
nvgpu_pbdma_status_is_chsw_switch(pbdma_status)) {
id = pbdma_status->next_id;
id_type = pbdma_status->next_id_type;
} else {
} else if (nvgpu_pbdma_status_ch_not_loaded(pbdma_status)) {
/* Nothing to do here */
nvgpu_err(g, "Invalid pbdma_status.id");
return;
nvgpu_log_info(g, "no channel loaded on pbdma.");
goto out;
} else {
nvgpu_err(g, "pbdma status not valid");
err = -EINVAL;
goto out;
}
if (id_type == PBDMA_STATUS_ID_TYPE_TSGID) {
@@ -128,7 +140,8 @@ void nvgpu_rc_pbdma_fault(struct gk20a *g, u32 pbdma_id, u32 error_notifier,
struct nvgpu_tsg *tsg;
if (ch == NULL) {
nvgpu_err(g, "channel is not referenceable");
return;
err = -EINVAL;
goto out;
}
tsg = nvgpu_tsg_from_ch(ch);
@@ -138,12 +151,21 @@ void nvgpu_rc_pbdma_fault(struct gk20a *g, u32 pbdma_id, u32 error_notifier,
RC_TYPE_PBDMA_FAULT);
} else {
nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid);
err = -EINVAL;
}
nvgpu_channel_put(ch);
} else {
nvgpu_err(g, "Invalid pbdma_status.id_type");
nvgpu_err(g, "Invalid pbdma_status id_type or next_id_type");
err = -EINVAL;
}
out:
if (err != 0) {
nvgpu_sw_quiesce(g);
}
return err;
}
void nvgpu_rc_runlist_update(struct gk20a *g, u32 runlist_id)