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gpu: nvgpu: add BVEC test for nvgpu_rc_pbdma_fault
Update nvgpu_rc_pbdma_fault with invalid checks and add BVEC test for it. Make ga10b_fifo_pbdma_isr static. NVGPU-6772 Change-Id: I5485760c53e1fff1278557a5b25659a1fc0e4eaf Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551617 (cherry picked from commit e917042d395d07cb902580bad3d5a7d0096cc303) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2623625 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -27,7 +27,7 @@
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struct nvgpu_channel;
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enum {
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enum nvgpu_err_notif {
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NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT = 0,
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NVGPU_ERR_NOTIFIER_GR_ERROR_SW_METHOD,
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NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY,
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@@ -40,6 +40,7 @@ enum {
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NVGPU_ERR_NOTIFIER_RESETCHANNEL_VERIF_ERROR,
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NVGPU_ERR_NOTIFIER_PBDMA_PUSHBUFFER_CRC_MISMATCH,
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NVGPU_ERR_NOTIFIER_CE_ERROR,
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NVGPU_ERR_NOTIFIER_INVAL,
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};
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void nvgpu_set_err_notifier_locked(struct nvgpu_channel *ch, u32 error);
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -51,7 +51,7 @@ struct gops_pbdma {
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bool (*handle_intr_1)(struct gk20a *g,
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u32 pbdma_id, u32 pbdma_intr_1,
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u32 *error_notifier);
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void (*handle_intr)(struct gk20a *g, u32 pbdma_id, bool recover);
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int (*handle_intr)(struct gk20a *g, u32 pbdma_id, bool recover);
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u32 (*set_clear_intr_offsets) (struct gk20a *g,
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u32 set_clear_size);
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u32 (*get_signature)(struct gk20a *g);
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -150,6 +150,17 @@ bool nvgpu_pbdma_status_is_chsw_save(struct nvgpu_pbdma_status_info
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*/
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bool nvgpu_pbdma_status_is_chsw_valid(struct nvgpu_pbdma_status_info
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*pbdma_status);
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/**
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* @brief Check if chsw_status is set to invalid.
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*
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* @param pbdma_status [in] Pointer to struct containing pbdma_status h/w
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* reg/field value.
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*
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* @return Interprets #pbdma_status and returns true if channel
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* status is set to #NVGPU_PBDMA_CHSW_STATUS_INVALID else returns false.
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*/
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bool nvgpu_pbdma_status_ch_not_loaded(struct nvgpu_pbdma_status_info
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*pbdma_status);
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/**
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* @brief Check if id_type is tsg.
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*
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@@ -103,6 +103,7 @@ struct nvgpu_tsg;
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struct nvgpu_channel;
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struct nvgpu_pbdma_status_info;
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struct mmu_fault_info;
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enum nvgpu_err_notif;
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static inline const char *nvgpu_rc_type_to_str(unsigned int rc_type)
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{
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@@ -172,8 +173,16 @@ void nvgpu_rc_ctxsw_timeout(struct gk20a *g, u32 eng_bitmask,
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*
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* Do PBDMA fault recovery. Set error notifier as per \a error_notifier and call
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* \a nvgpu_rc_tsg_and_related_engines to do the recovery.
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*
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* @return 0 in case of success, < 0 in case of failure.
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* @retval -EINVAL in case of following cases:
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* 1. the error_notifier is invalid.
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* 2. the pbdma status is invalid.
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* 3. the channel is not referenceable.
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* 4. the channel is not bound to tsg.
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* 5. the id type or next_id type are not indicating channel id type or tsg id type.
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*/
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void nvgpu_rc_pbdma_fault(struct gk20a *g, u32 pbdma_id, u32 error_notifier,
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int nvgpu_rc_pbdma_fault(struct gk20a *g, u32 pbdma_id, enum nvgpu_err_notif error_notifier,
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struct nvgpu_pbdma_status_info *pbdma_status);
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/**
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