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gpu: nvgpu: support userspace Read Only mappings
Until now, all userspace buffers were mapped in the GMMU as Read & Write
(RW) by default. In order to enable the use cases which require the GPU
to only read the SYSMEM buffers and not inadvertently write to those,
map buffer ioctls need to provide interface to set the mapping access
type from the userspace.
Some of the use cases are:
1. A third party server process exposes shared memory that is
read-only to the client process, which does the GPU processing.
Registering this memory using cudaHostRegister API as read-only
in the client process will restict the access to Read Only type
from the GPU.
2. IO devices exposing streaming read-only data for processing by
the GPU.
3. For marking semantically read-only data as actually read-only
for the purposes of debugging data corruption.
This patch introduces new AS buffer mapping bitmask flag and
corresponding core VM mapping bitmask flag for representing
Read Only (RO) access type. By default, the access is set
as Read Write (RW).
Bug 200621157
Change-Id: I5ec9dec3ce089e577b86c43003d92b61eee4a90b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2361750
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
committed by
Alex Waterman
parent
1182a49f5c
commit
8156a23a6e
@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* under the terms and conditions of the GNU General Public License,
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@@ -60,7 +60,6 @@ int nvgpu_vm_map_linux(struct vm_gk20a *vm,
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u32 page_size,
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u32 page_size,
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s16 compr_kind,
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s16 compr_kind,
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s16 incompr_kind,
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s16 incompr_kind,
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enum gk20a_mem_rw_flag rw_flag,
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u64 buffer_offset,
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u64 buffer_offset,
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u64 mapping_size,
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u64 mapping_size,
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struct vm_gk20a_mapping_batch *mapping_batch,
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struct vm_gk20a_mapping_batch *mapping_batch,
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* copy of this software and associated documentation files (the "Software"),
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@@ -339,6 +339,7 @@ struct vm_gk20a {
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#define NVGPU_VM_MAP_DIRECT_KIND_CTRL BIT32(4)
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#define NVGPU_VM_MAP_DIRECT_KIND_CTRL BIT32(4)
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#define NVGPU_VM_MAP_L3_ALLOC BIT32(5)
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#define NVGPU_VM_MAP_L3_ALLOC BIT32(5)
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#define NVGPU_VM_MAP_PLATFORM_ATOMIC BIT32(6)
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#define NVGPU_VM_MAP_PLATFORM_ATOMIC BIT32(6)
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#define NVGPU_VM_MAP_ACCESS_NO_WRITE BIT32(7)
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#define NVGPU_KIND_INVALID S16(-1)
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#define NVGPU_KIND_INVALID S16(-1)
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@@ -1111,7 +1111,6 @@ __releases(&l->cde_app->mutex)
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map_size),
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map_size),
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NV_KIND_INVALID,
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NV_KIND_INVALID,
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compbits_kind, /* incompressible kind */
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compbits_kind, /* incompressible kind */
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gk20a_mem_flag_none,
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map_offset, map_size,
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map_offset, map_size,
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NULL,
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NULL,
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&map_vaddr);
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&map_vaddr);
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@@ -58,6 +58,8 @@ static u32 nvgpu_vm_translate_linux_flags(struct gk20a *g, u32 flags)
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core_flags |= NVGPU_VM_MAP_DIRECT_KIND_CTRL;
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core_flags |= NVGPU_VM_MAP_DIRECT_KIND_CTRL;
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if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC)
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if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC)
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core_flags |= NVGPU_VM_MAP_PLATFORM_ATOMIC;
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core_flags |= NVGPU_VM_MAP_PLATFORM_ATOMIC;
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if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_ACCESS_NO_WRITE)
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core_flags |= NVGPU_VM_MAP_ACCESS_NO_WRITE;
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if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS)
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if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS)
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nvgpu_warn(g, "Ignoring deprecated flag: "
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nvgpu_warn(g, "Ignoring deprecated flag: "
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@@ -188,12 +190,12 @@ int nvgpu_vm_map_linux(struct vm_gk20a *vm,
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u32 page_size,
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u32 page_size,
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s16 compr_kind,
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s16 compr_kind,
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s16 incompr_kind,
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s16 incompr_kind,
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enum gk20a_mem_rw_flag rw_flag,
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u64 buffer_offset,
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u64 buffer_offset,
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u64 mapping_size,
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u64 mapping_size,
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struct vm_gk20a_mapping_batch *batch,
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struct vm_gk20a_mapping_batch *batch,
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u64 *gpu_va)
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u64 *gpu_va)
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{
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{
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enum gk20a_mem_rw_flag rw_flag = gk20a_mem_flag_none;
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struct gk20a *g = gk20a_from_vm(vm);
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struct gk20a *g = gk20a_from_vm(vm);
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struct device *dev = dev_from_gk20a(g);
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struct device *dev = dev_from_gk20a(g);
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struct nvgpu_os_buffer os_buf;
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struct nvgpu_os_buffer os_buf;
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@@ -223,6 +225,10 @@ int nvgpu_vm_map_linux(struct vm_gk20a *vm,
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goto clean_up;
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goto clean_up;
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}
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}
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if (flags & NVGPU_VM_MAP_ACCESS_NO_WRITE) {
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rw_flag = gk20a_mem_flag_read_only;
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}
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err = nvgpu_vm_map(vm,
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err = nvgpu_vm_map(vm,
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&os_buf,
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&os_buf,
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nvgpu_sgt,
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nvgpu_sgt,
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@@ -328,7 +334,6 @@ int nvgpu_vm_map_buffer(struct vm_gk20a *vm,
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nvgpu_vm_translate_linux_flags(g, flags),
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nvgpu_vm_translate_linux_flags(g, flags),
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page_size,
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page_size,
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compr_kind, incompr_kind,
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compr_kind, incompr_kind,
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gk20a_mem_flag_none,
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buffer_offset,
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buffer_offset,
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mapping_size,
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mapping_size,
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batch,
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batch,
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@@ -1918,6 +1918,7 @@ struct nvgpu_as_bind_channel_args {
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#define NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC (1 << 7)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC (1 << 7)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL (1 << 8)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL (1 << 8)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC (1 << 9)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC (1 << 9)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_ACCESS_NO_WRITE (1 << 10)
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/*
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/*
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* VM map buffer IOCTL
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* VM map buffer IOCTL
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