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gpu: nvgpu: gp10x: initial support for vidmem apertures

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add gk20a_aperture_mask() for memory target selection now that buffers
can actually be allocated from vidmem, and use it in all cases that have
a mem_desc available.

Jira DNVGPU-76

Change-Id: Ifd1908808d928155a0cadeff8ca451a151bfc8c5
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1169294
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Konsta Holtta
2016-06-17 15:45:17 +03:00
committed by Deepak Nibade
parent 6e1428484e
commit 81756640cb
1 changed files with 10 additions and 8 deletions
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18
drivers/gpu/nvgpu/gp10b/mm_gp10b.c
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@@ -33,7 +33,6 @@ static int gp10b_init_mm_setup_hw(struct gk20a *g)
{ {
struct mm_gk20a *mm = &g->mm; struct mm_gk20a *mm = &g->mm;
struct mem_desc *inst_block = &mm->bar1.inst_block; struct mem_desc *inst_block = &mm->bar1.inst_block;
u64 inst_pa = gk20a_mm_inst_block_addr(g, inst_block);
int err = 0; int err = 0;
gk20a_dbg_fn(""); gk20a_dbg_fn("");
@@ -44,7 +43,7 @@ static int gp10b_init_mm_setup_hw(struct gk20a *g)
(g->ops.mm.get_iova_addr(g, g->mm.sysmem_flush.sgt->sgl, 0) (g->ops.mm.get_iova_addr(g, g->mm.sysmem_flush.sgt->sgl, 0)
>> 8ULL)); >> 8ULL));
g->ops.mm.bar1_bind(g, inst_pa); g->ops.mm.bar1_bind(g, inst_block);
if (g->ops.mm.init_bar2_mm_hw_setup) { if (g->ops.mm.init_bar2_mm_hw_setup) {
err = g->ops.mm.init_bar2_mm_hw_setup(g); err = g->ops.mm.init_bar2_mm_hw_setup(g);
@@ -378,21 +377,24 @@ static const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g,
return gp10b_mm_levels; return gp10b_mm_levels;
} }
static void gp10b_mm_init_pdb(struct gk20a *g, struct mem_desc *mem, static void gp10b_mm_init_pdb(struct gk20a *g, struct mem_desc *inst_block,
u64 pdb_addr) struct vm_gk20a *vm)
{ {
u64 pdb_addr = g->ops.mm.get_iova_addr(g, vm->pdb.mem.sgt->sgl, 0);
u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
u32 pdb_addr_hi = u64_hi32(pdb_addr); u32 pdb_addr_hi = u64_hi32(pdb_addr);
gk20a_mem_wr32(g, mem, ram_in_page_dir_base_lo_w(), gk20a_dbg_info("pde pa=0x%llx", pdb_addr);
(g->mm.vidmem_is_vidmem ?
ram_in_page_dir_base_target_sys_mem_ncoh_f() : gk20a_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(),
gk20a_aperture_mask(g, &vm->pdb.mem,
ram_in_page_dir_base_target_sys_mem_ncoh_f(),
ram_in_page_dir_base_target_vid_mem_f()) | ram_in_page_dir_base_target_vid_mem_f()) |
ram_in_page_dir_base_vol_true_f() | ram_in_page_dir_base_vol_true_f() |
ram_in_page_dir_base_lo_f(pdb_addr_lo) | ram_in_page_dir_base_lo_f(pdb_addr_lo) |
1 << 10); 1 << 10);
gk20a_mem_wr32(g, mem, ram_in_page_dir_base_hi_w(), gk20a_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(),
ram_in_page_dir_base_hi_f(pdb_addr_hi)); ram_in_page_dir_base_hi_f(pdb_addr_hi));
} }