From 81d95456b92888d35dae3016523f8f2f50835a15 Mon Sep 17 00:00:00 2001 From: Martin Radev Date: Mon, 27 Feb 2023 15:03:29 +0200 Subject: [PATCH] gpu: nvgpu: Rename PLATFORM_ATOMIC to SYSTEM_COHERENT To support current and future usecases, it would be beneficial to select the SYSTEM_COHERENT aperture explicitly. The benefits are: - platform atomic code is cleaned-up. - userspace can select the SYSTEM_COHERENT aperture for any specific usecases. Bug 3959027 Change-Id: I6489ebe87fa75cc760930277bad5e0cacca80eb6 Signed-off-by: Martin Radev Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2864177 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: svc-mobile-misra Reviewed-by: Seema Khowala GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/common/fifo/priv_cmdbuf.c | 4 +-- drivers/gpu/nvgpu/common/mm/gmmu/page_table.c | 6 ++-- drivers/gpu/nvgpu/common/mm/gmmu/pte.c | 13 ++------ drivers/gpu/nvgpu/common/mm/nvgpu_mem.c | 12 +++---- drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.c | 6 ++-- drivers/gpu/nvgpu/hal/init/hal_ga100.c | 1 - drivers/gpu/nvgpu/hal/init/hal_ga10b.c | 1 - drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 1 - drivers/gpu/nvgpu/hal/init/hal_tu104.c | 1 - .../gpu/nvgpu/hal/mm/gmmu/gmmu_ga10b_fusa.c | 5 ++- drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gk20a.c | 5 +-- .../gpu/nvgpu/hal/mm/gmmu/gmmu_gp10b_fusa.c | 5 ++- .../gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c | 1 - .../gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c | 1 - drivers/gpu/nvgpu/include/nvgpu/enabled.h | 2 -- drivers/gpu/nvgpu/include/nvgpu/gmmu.h | 18 +++++------ drivers/gpu/nvgpu/include/nvgpu/gops/mm.h | 2 +- .../gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/vm.h | 6 ++-- drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 2 +- drivers/gpu/nvgpu/os/linux/linux-dma.c | 4 +-- drivers/gpu/nvgpu/os/linux/nvgpu_mem.c | 8 ++--- drivers/gpu/nvgpu/os/linux/vm.c | 23 ++++++++++---- drivers/gpu/nvgpu/os/posix/posix-nvgpu_mem.c | 4 +-- include/uapi/linux/nvgpu-as.h | 7 +++-- .../gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.c | 31 ++++++++++--------- .../gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.h | 4 +-- 27 files changed, 84 insertions(+), 91 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fifo/priv_cmdbuf.c b/drivers/gpu/nvgpu/common/fifo/priv_cmdbuf.c index 44a0552f8..335bfade4 100644 --- a/drivers/gpu/nvgpu/common/fifo/priv_cmdbuf.c +++ b/drivers/gpu/nvgpu/common/fifo/priv_cmdbuf.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -325,7 +325,7 @@ void nvgpu_priv_cmdbuf_finish(struct gk20a *g, struct priv_cmd_entry *e, nvgpu_assert(e->fill_off == e->size); #ifdef CONFIG_NVGPU_TRACE - if (e->mem->aperture == APERTURE_SYSMEM) { + if (nvgpu_aperture_is_sysmem(e->mem->aperture)) { trace_gk20a_push_cmdbuf(g->name, 0, e->size, 0, (u32 *)e->mem->cpu_va + e->off); } diff --git a/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c b/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c index bbdbf2637..46138e126 100644 --- a/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c +++ b/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c @@ -924,7 +924,7 @@ static void nvgpu_gmmu_update_page_table_dbg_print(struct gk20a *g, "vm=%s " "%-5s GPU virt %#-12llx +%#-9llx phys %#-12llx " "phys offset: %#-4llx; pgsz: %3dkb perm=%-2s | " - "kind=%#02x APT=%-6s %c%c%c%c%c", + "kind=%#02x APT=%-6s %c%c%c%c", vm->name, (sgt != NULL) ? "MAP" : "UNMAP", virt_addr, @@ -939,8 +939,7 @@ static void nvgpu_gmmu_update_page_table_dbg_print(struct gk20a *g, attrs->cacheable ? 'C' : '-', attrs->sparse ? 'S' : '-', attrs->priv ? 'P' : '-', - attrs->valid ? 'V' : '-', - attrs->platform_atomic ? 'A' : '-'); + attrs->valid ? 'V' : '-'); #else (void)g; (void)attrs; @@ -1046,7 +1045,6 @@ u64 nvgpu_gmmu_map_locked(struct vm_gk20a *vm, .priv = priv, .valid = (flags & NVGPU_VM_MAP_UNMAPPED_PTE) == 0U, .aperture = aperture, - .platform_atomic = (flags & NVGPU_VM_MAP_PLATFORM_ATOMIC) != 0U }; #ifdef CONFIG_NVGPU_COMPRESSION u64 ctag_granularity = g->ops.fb.compression_page_size(g); diff --git a/drivers/gpu/nvgpu/common/mm/gmmu/pte.c b/drivers/gpu/nvgpu/common/mm/gmmu/pte.c index 870e137ff..19510525b 100644 --- a/drivers/gpu/nvgpu/common/mm/gmmu/pte.c +++ b/drivers/gpu/nvgpu/common/mm/gmmu/pte.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -41,16 +41,10 @@ u32 nvgpu_gmmu_default_big_page_size(void) */ u32 nvgpu_gmmu_aperture_mask(struct gk20a *g, enum nvgpu_aperture mem_ap, - bool platform_atomic_attr, u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask) { - if (nvgpu_is_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC) && - platform_atomic_attr) { - mem_ap = APERTURE_SYSMEM_COH; - } - return nvgpu_aperture_mask_raw(g, mem_ap, sysmem_mask, sysmem_coh_mask, @@ -63,8 +57,7 @@ static char *map_attrs_to_str(char *dest, struct nvgpu_gmmu_attrs *attrs) dest[1] = attrs->sparse ? 'S' : '-'; dest[2] = attrs->priv ? 'P' : '-'; dest[3] = attrs->valid ? 'V' : '-'; - dest[4] = attrs->platform_atomic ? 'A' : '-'; - dest[5] = '\0'; + dest[4] = '\0'; return dest; } @@ -74,7 +67,7 @@ void nvgpu_pte_dbg_print(struct gk20a *g, const char *vm_name, u32 pd_idx, u32 mmu_level_entry_size, u64 virt_addr, u64 phys_addr, u32 page_size, u32 *pte_w) { - char attrs_str[6]; + char attrs_str[5]; char ctag_str[32] = "\0"; const char *aperture_str = nvgpu_aperture_str(attrs->aperture); const char *perm_str = nvgpu_gmmu_perm_str(attrs->rw_flag); diff --git a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c index 2a78e6e20..69505b6ff 100644 --- a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c +++ b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -107,7 +107,7 @@ u32 nvgpu_mem_rd32(struct gk20a *g, struct nvgpu_mem *mem, u64 w) { u32 data = 0; - if (mem->aperture == APERTURE_SYSMEM) { + if (nvgpu_aperture_is_sysmem(mem->aperture)) { u32 *ptr = mem->cpu_va; WARN_ON(ptr == NULL); @@ -146,7 +146,7 @@ void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem, WARN_ON((offset & 3ULL) != 0ULL); WARN_ON((size & 3ULL) != 0ULL); - if (mem->aperture == APERTURE_SYSMEM) { + if (nvgpu_aperture_is_sysmem(mem->aperture)) { u8 *src = (u8 *)mem->cpu_va + offset; WARN_ON(mem->cpu_va == NULL); @@ -164,7 +164,7 @@ void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem, void nvgpu_mem_wr32(struct gk20a *g, struct nvgpu_mem *mem, u64 w, u32 data) { - if (mem->aperture == APERTURE_SYSMEM) { + if (nvgpu_aperture_is_sysmem(mem->aperture)) { u32 *ptr = mem->cpu_va; WARN_ON(ptr == NULL); @@ -197,7 +197,7 @@ void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u64 offset, WARN_ON((offset & 3ULL) != 0ULL); WARN_ON((size & 3ULL) != 0ULL); - if (mem->aperture == APERTURE_SYSMEM) { + if (nvgpu_aperture_is_sysmem(mem->aperture)) { u8 *dest = (u8 *)mem->cpu_va + offset; WARN_ON(mem->cpu_va == NULL); @@ -225,7 +225,7 @@ void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u64 offset, c &= 0xffU; - if (mem->aperture == APERTURE_SYSMEM) { + if (nvgpu_aperture_is_sysmem(mem->aperture)) { u8 *dest = (u8 *)mem->cpu_va + offset; WARN_ON(mem->cpu_va == NULL); diff --git a/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.c index 044e6bd52..c9a221b31 100644 --- a/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.c @@ -1,7 +1,7 @@ /* * Virtualized GPU Memory Management * - * Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -358,8 +358,8 @@ u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm, if (flags & NVGPU_VM_MAP_L3_ALLOC) { p->flags |= TEGRA_VGPU_MAP_L3_ALLOC; } - if (flags & NVGPU_VM_MAP_PLATFORM_ATOMIC) { - p->flags |= TEGRA_VGPU_MAP_PLATFORM_ATOMIC; + if (flags & NVGPU_VM_MAP_SYSTEM_COHERENT) { + p->flags |= TEGRA_VGPU_MAP_SYSTEM_COHERENT; } p->prot = prot; diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c index 7203a0531..8c60e01c3 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c @@ -1942,7 +1942,6 @@ int ga100_init_hal(struct gk20a *g) #ifdef CONFIG_NVGPU_GFXP nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, true); #endif - nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_SEC2_VM, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_GSP_VM, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_PMU_SUPER_SURFACE, true); diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index 9b0be3ea1..3e7562f95 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -1984,7 +1984,6 @@ int ga10b_init_hal(struct gk20a *g) #ifdef CONFIG_NVGPU_GFXP nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, true); #endif - nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, true); #ifdef CONFIG_NVGPU_PROFILER nvgpu_set_enabled(g, NVGPU_SUPPORT_VAB_ENABLED, true); diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index b8a63ecbd..9ac623e22 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -1674,7 +1674,6 @@ int gv11b_init_hal(struct gk20a *g) #ifdef CONFIG_NVGPU_GFXP nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, true); #endif - nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, true); #ifdef CONFIG_KMD_SCHEDULING_WORKER_THREAD diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index eb2184b83..0bf5b15ae 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -1853,7 +1853,6 @@ int tu104_init_hal(struct gk20a *g) #ifdef CONFIG_NVGPU_GFXP nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, true); #endif - nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_SEC2_VM, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_GSP_VM, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_PMU_SUPER_SURFACE, true); diff --git a/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_ga10b_fusa.c index 1b08df7c1..bcb0ecd7e 100644 --- a/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_ga10b_fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -197,12 +197,11 @@ static void ga10b_update_pte(struct vm_gk20a *vm, gmmu_new_pte_valid_true_f() : gmmu_new_pte_valid_false_f(); u64 phys_shifted = phys_addr >> gmmu_new_pte_address_shift_v(); - u32 pte_addr = (attrs->aperture == APERTURE_SYSMEM) ? + u32 pte_addr = nvgpu_aperture_is_sysmem(attrs->aperture) ? gmmu_new_pte_address_sys_f(u64_lo32(phys_shifted)) : gmmu_new_pte_address_vid_f(u64_lo32(phys_shifted)); u32 pte_tgt = nvgpu_gmmu_aperture_mask(g, attrs->aperture, - attrs->platform_atomic, gmmu_new_pte_aperture_sys_mem_ncoh_f(), gmmu_new_pte_aperture_sys_mem_coh_f(), gmmu_new_pte_aperture_video_memory_f()); diff --git a/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gk20a.c b/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gk20a.c index 7b1d34c51..5fc3b312a 100644 --- a/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gk20a.c +++ b/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gk20a.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -23,6 +23,7 @@ #include #include #include +#include #include @@ -116,7 +117,7 @@ static void update_pte(struct vm_gk20a *vm, gmmu_pte_valid_true_f() : gmmu_pte_valid_false_f(); u32 phys_shifted = U32(phys_addr >> gmmu_pte_address_shift_v()); - u32 addr = attrs->aperture == APERTURE_SYSMEM ? + u32 addr = nvgpu_aperture_is_sysmem(attrs->aperture) ? gmmu_pte_address_sys_f(phys_shifted) : gmmu_pte_address_vid_f(phys_shifted); #ifdef CONFIG_NVGPU_COMPRESSION diff --git a/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gp10b_fusa.c index f46713202..235b721b8 100644 --- a/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gp10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gp10b_fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -162,12 +162,11 @@ static void update_pte(struct vm_gk20a *vm, gmmu_new_pte_valid_true_f() : gmmu_new_pte_valid_false_f(); u64 phys_shifted = phys_addr >> gmmu_new_pte_address_shift_v(); - u32 pte_addr = (attrs->aperture == APERTURE_SYSMEM) ? + u32 pte_addr = nvgpu_aperture_is_sysmem(attrs->aperture) ? gmmu_new_pte_address_sys_f(u64_lo32(phys_shifted)) : gmmu_new_pte_address_vid_f(u64_lo32(phys_shifted)); u32 pte_tgt = nvgpu_gmmu_aperture_mask(g, attrs->aperture, - attrs->platform_atomic, gmmu_new_pte_aperture_sys_mem_ncoh_f(), gmmu_new_pte_aperture_sys_mem_coh_f(), gmmu_new_pte_aperture_video_memory_f()); diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c index c3b17dffe..b9f8f3610 100644 --- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c @@ -197,7 +197,6 @@ static int vgpu_ga10b_init_gpu_characteristics(struct gk20a *g) nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, true); #endif nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, true); - nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, true); #ifdef CONFIG_NVGPU_FECS_TRACE nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true); diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c index 183d60bd7..5c897e5ab 100644 --- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c @@ -178,7 +178,6 @@ static int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g) nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, true); #endif nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, true); - nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, true); return 0; diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index e75320c00..dc90caa55 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h @@ -163,8 +163,6 @@ struct gk20a; DEFINE_FLAG(NVGPU_SUPPORT_SEC2_RTOS, "SEC2 RTOS support"), \ DEFINE_FLAG(NVGPU_SUPPORT_PMU_RTOS_FBQ, "PMU RTOS FBQ support"),\ DEFINE_FLAG(NVGPU_SUPPORT_ZBC_STENCIL, "ZBC STENCIL support"), \ - DEFINE_FLAG(NVGPU_SUPPORT_PLATFORM_ATOMIC, \ - "PLATFORM_ATOMIC support"), \ DEFINE_FLAG(NVGPU_SUPPORT_SEC2_VM, "SEC2 VM support"), \ DEFINE_FLAG(NVGPU_SUPPORT_GSP_VM, "GSP VM support"), \ DEFINE_FLAG(NVGPU_SUPPORT_PREEMPTION_GFXP, \ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h index c6ea38051..aec41ef68 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -80,8 +80,9 @@ enum nvgpu_aperture { */ APERTURE_SYSMEM, /** - * This coherent memory is located in SYSMEM. Note: This type is used - * internally. Use APERTURE_SYSMEM. + * This coherent memory is located in SYSMEM. Note: This aperture is + * is used only for few special cases. Clients should normally use + * APERTURE_SYSMEM. */ APERTURE_SYSMEM_COH, /** @@ -179,10 +180,6 @@ struct nvgpu_gmmu_attrs { * True if tegra_raw flag is valid. */ bool tegra_raw; - /** - * True if platform_atomic flag is valid. - */ - bool platform_atomic; }; /** @@ -289,7 +286,7 @@ int nvgpu_gmmu_init_page_table(struct vm_gk20a *vm); * @param size [in] Size of the mapping in bytes. * @param flags [in] Mapping flags. * - Min: NVGPU_VM_MAP_FIXED_OFFSET - * - Max: NVGPU_VM_MAP_PLATFORM_ATOMIC + * - Max: NVGPU_VM_MAP_SYSTEM_COHERENT * @param rw_flag [in] Flag designates the requested GMMU mapping. * - Min: gk20a_mem_flag_none * - Max: gk20a_mem_flag_write_only @@ -358,7 +355,7 @@ u64 nvgpu_gmmu_map(struct vm_gk20a *vm, * @param size [in] Size of the buffer in bytes. * @param flags [in] Mapping flags. * - Min: NVGPU_VM_MAP_FIXED_OFFSET - * - Max: NVGPU_VM_MAP_PLATFORM_ATOMIC + * - Max: NVGPU_VM_MAP_SYSTEM_COHERENT * @param rw_flag [in] Flag designates the requested GMMU mapping. * - Min: gk20a_mem_flag_none * - Max: gk20a_mem_flag_write_only @@ -515,7 +512,7 @@ int nvgpu_set_pte(struct gk20a *g, struct vm_gk20a *vm, u64 vaddr, u32 *pte); * @param ctag_offset [in] Size of the buffer in bytes. * @param flags [in] Mapping flags. * - Min: NVGPU_VM_MAP_FIXED_OFFSET - * - Max: NVGPU_VM_MAP_PLATFORM_ATOMIC + * - Max: NVGPU_VM_MAP_SYSTEM_COHERENT * @param rw_flag [in] Flag designates the requested GMMU mapping. * - Min: gk20a_mem_flag_none * - Max: gk20a_mem_flag_write_only @@ -633,7 +630,6 @@ u32 nvgpu_gmmu_default_big_page_size(void); u32 nvgpu_gmmu_aperture_mask(struct gk20a *g, enum nvgpu_aperture mem_ap, - bool platform_atomic_attr, u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/mm.h b/drivers/gpu/nvgpu/include/nvgpu/gops/mm.h index 7384280ff..c9b2c8bb6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/mm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/mm.h @@ -215,7 +215,7 @@ struct gops_mm_gmmu { * @param ctag_offset [in] Size of the buffer in bytes. * @param flags [in] Mapping flags. * Min:NVGPU_VM_MAP_FIXED_OFFSET - * Max:NVGPU_VM_MAP_PLATFORM_ATOMIC + * Max:NVGPU_VM_MAP_SYSTEM_COHERENT * @param rw_flag [in] Flag designates the requested * GMMU mapping. * @param clear_ctags [in] True if ctags clear is required. diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h index a6be3bd12..88e85860d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h @@ -181,7 +181,7 @@ struct tegra_vgpu_as_map_params { #define TEGRA_VGPU_MAP_CACHEABLE (1 << 0) #define TEGRA_VGPU_MAP_IO_COHERENT (1 << 1) #define TEGRA_VGPU_MAP_L3_ALLOC (1 << 2) -#define TEGRA_VGPU_MAP_PLATFORM_ATOMIC (1 << 3) +#define TEGRA_VGPU_MAP_SYSTEM_COHERENT (1 << 3) struct tegra_vgpu_as_map_ex_params { u64 handle; diff --git a/drivers/gpu/nvgpu/include/nvgpu/vm.h b/drivers/gpu/nvgpu/include/nvgpu/vm.h index 4957c4f77..77c4d8703 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vm.h @@ -350,7 +350,7 @@ struct vm_gk20a { #define NVGPU_VM_MAP_IO_COHERENT BIT32(2) #define NVGPU_VM_MAP_UNMAPPED_PTE BIT32(3) #define NVGPU_VM_MAP_L3_ALLOC BIT32(5) -#define NVGPU_VM_MAP_PLATFORM_ATOMIC BIT32(6) +#define NVGPU_VM_MAP_SYSTEM_COHERENT BIT32(6) #define NVGPU_VM_MAP_TEGRA_RAW BIT32(7) #define NVGPU_VM_MAP_ACCESS_DEFAULT 0U @@ -536,7 +536,7 @@ void nvgpu_vm_put_buffers(struct vm_gk20a *vm, * fixed mappings. * @param flags [in] Flags describes the properties of the mapping. * - Min: NVGPU_VM_MAP_FIXED_OFFSET - * - Max: NVGPU_VM_MAP_PLATFORM_ATOMIC + * - Max: NVGPU_VM_MAP_SYSTEM_COHERENT * @param kind [in] Kind parameter. * * - Acquire the vm.update_gmmu_lock. @@ -571,7 +571,7 @@ struct nvgpu_mapped_buf *nvgpu_vm_find_mapping(struct vm_gk20a *vm, * - Max: gk20a_mem_flag_write_only * @param flags [in] Mapping is fixed or not. * - Min: NVGPU_VM_MAP_FIXED_OFFSET - * - Max: NVGPU_VM_MAP_PLATFORM_ATOMIC + * - Max: NVGPU_VM_MAP_SYSTEM_COHERENT * @param compr_kind [in] Default map caching key. * @param incompr_kind [in] Map caching key. * @param batch [in] Describes TLB invalidation and cache diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index 131a903f2..8ff879473 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c @@ -2025,7 +2025,7 @@ static int nvgpu_dbg_get_context_buffer(struct gk20a *g, struct nvgpu_mem *ctx_m u32 offset = 0; #endif - if (ctx_mem->aperture == APERTURE_SYSMEM) { + if (nvgpu_aperture_is_sysmem(ctx_mem->aperture)) { if (ctx_mem->cpu_va == NULL) { nvgpu_err(g, "CPU pointer is NULL. Note that this feature is currently \ not supported on virtual GPU."); diff --git a/drivers/gpu/nvgpu/os/linux/linux-dma.c b/drivers/gpu/nvgpu/os/linux/linux-dma.c index 45f9830f8..aca9dede9 100644 --- a/drivers/gpu/nvgpu/os/linux/linux-dma.c +++ b/drivers/gpu/nvgpu/os/linux/linux-dma.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2023, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -364,7 +364,7 @@ int nvgpu_dma_mmap_sys(struct gk20a *g, struct vm_area_struct *vma, struct nvgpu return -EINVAL; } - if (mem->aperture != APERTURE_SYSMEM) { + if (!(nvgpu_aperture_is_sysmem(mem->aperture))) { return -EINVAL; } diff --git a/drivers/gpu/nvgpu/os/linux/nvgpu_mem.c b/drivers/gpu/nvgpu/os/linux/nvgpu_mem.c index e283dd370..9081c1f3b 100644 --- a/drivers/gpu/nvgpu/os/linux/nvgpu_mem.c +++ b/drivers/gpu/nvgpu/os/linux/nvgpu_mem.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2023, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -110,7 +110,7 @@ u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem) #ifdef CONFIG_NVGPU_DGPU struct nvgpu_page_alloc *alloc; - if (mem->aperture == APERTURE_SYSMEM) + if (nvgpu_aperture_is_sysmem(mem->aperture)) return nvgpu_mem_get_addr_sysmem(g, mem); /* @@ -123,7 +123,7 @@ u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem) return alloc->base; #else - if (mem->aperture == APERTURE_SYSMEM) + if (nvgpu_aperture_is_sysmem(mem->aperture)) return nvgpu_mem_get_addr_sysmem(g, mem); return 0; @@ -162,7 +162,7 @@ int nvgpu_mem_create_from_mem(struct gk20a *g, u64 size = nr_pages * NVGPU_CPU_PAGE_SIZE; dma_addr_t new_iova; - if (src->aperture != APERTURE_SYSMEM) + if (!nvgpu_aperture_is_sysmem(src->aperture)) return -EINVAL; /* Some silly things a caller might do... */ diff --git a/drivers/gpu/nvgpu/os/linux/vm.c b/drivers/gpu/nvgpu/os/linux/vm.c index 067f560f5..c6dcde6c3 100644 --- a/drivers/gpu/nvgpu/os/linux/vm.c +++ b/drivers/gpu/nvgpu/os/linux/vm.c @@ -72,14 +72,14 @@ static int nvgpu_vm_translate_linux_flags(struct gk20a *g, u32 flags, u32 *out_c if (!nvgpu_is_enabled(g, NVGPU_DISABLE_L3_SUPPORT)) core_flags |= NVGPU_VM_MAP_L3_ALLOC; } - if ((flags & NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC) != 0U) { - core_flags |= NVGPU_VM_MAP_PLATFORM_ATOMIC; - consumed_flags |= NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC; - } if ((flags & NVGPU_AS_MAP_BUFFER_FLAGS_TEGRA_RAW) != 0U) { core_flags |= NVGPU_VM_MAP_TEGRA_RAW; consumed_flags |= NVGPU_AS_MAP_BUFFER_FLAGS_TEGRA_RAW; } + if ((flags & NVGPU_AS_MAP_BUFFER_FLAGS_SYSTEM_COHERENT) != 0U) { + core_flags |= NVGPU_VM_MAP_SYSTEM_COHERENT; + consumed_flags |= NVGPU_AS_MAP_BUFFER_FLAGS_SYSTEM_COHERENT; + } if ((flags & NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS) != 0U) { nvgpu_warn(g, "Ignoring deprecated flag: " "NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS"); @@ -280,6 +280,7 @@ int nvgpu_vm_map_linux(struct vm_gk20a *vm, struct nvgpu_sgt *nvgpu_sgt = NULL; struct nvgpu_mapped_buf *mapped_buffer = NULL; struct dma_buf_attachment *attachment; + enum nvgpu_aperture buffer_aperture; int err = 0; nvgpu_log(g, gpu_dbg_map, "dmabuf file mode: 0x%x mapping flags: 0x%x", @@ -305,11 +306,21 @@ int nvgpu_vm_map_linux(struct vm_gk20a *vm, os_buf.attachment = attachment; os_buf.dev = dev; - if (gk20a_dmabuf_aperture(g, dmabuf) == APERTURE_INVALID) { + buffer_aperture = gk20a_dmabuf_aperture(g, dmabuf); + if (buffer_aperture == APERTURE_INVALID) { err = -EINVAL; goto clean_up; } + if ((flags & NVGPU_VM_MAP_SYSTEM_COHERENT) != 0U) { + if (buffer_aperture == APERTURE_VIDMEM) { + nvgpu_err(g, "Vidmem buffers cannot be mapped into the SYSTEM_COHERENT aperture"); + err = -EINVAL; + goto clean_up; + } + buffer_aperture = APERTURE_SYSMEM_COH; + } + nvgpu_sgt = nvgpu_linux_sgt_create(g, sgt); if (!nvgpu_sgt) { err = -ENOMEM; @@ -328,7 +339,7 @@ int nvgpu_vm_map_linux(struct vm_gk20a *vm, compr_kind, incompr_kind, batch, - gk20a_dmabuf_aperture(g, dmabuf), + buffer_aperture, &mapped_buffer); nvgpu_sgt_free(g, nvgpu_sgt); diff --git a/drivers/gpu/nvgpu/os/posix/posix-nvgpu_mem.c b/drivers/gpu/nvgpu/os/posix/posix-nvgpu_mem.c index a9b80536f..47a2664c1 100644 --- a/drivers/gpu/nvgpu/os/posix/posix-nvgpu_mem.c +++ b/drivers/gpu/nvgpu/os/posix/posix-nvgpu_mem.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -305,7 +305,7 @@ int nvgpu_mem_create_from_mem(struct gk20a *g, (void)g; - if (src->aperture != APERTURE_SYSMEM) { + if (!nvgpu_aperture_is_sysmem(src->aperture)) { return -EINVAL; } diff --git a/include/uapi/linux/nvgpu-as.h b/include/uapi/linux/nvgpu-as.h index 54fe108e2..781a51397 100644 --- a/include/uapi/linux/nvgpu-as.h +++ b/include/uapi/linux/nvgpu-as.h @@ -108,7 +108,7 @@ struct nvgpu_as_bind_channel_args { #define NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE (1 << 5) #define NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS (1 << 6) #define NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC (1 << 7) -#define NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC (1 << 9) +#define NVGPU_AS_MAP_BUFFER_FLAGS_SYSTEM_COHERENT (1 << 9) #define NVGPU_AS_MAP_BUFFER_FLAGS_TEGRA_RAW (1 << 12) #define NVGPU_AS_MAP_BUFFER_FLAGS_ACCESS_BITMASK_OFFSET 10U @@ -160,9 +160,10 @@ struct nvgpu_as_bind_channel_args { * * Deprecated. * - * %NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC + * %NVGPU_AS_MAP_BUFFER_FLAGS_SYSTEM_COHERENT * - * Specify that a mapping should use platform atomics. + * Specify that a mapping should use the system coherent aperture. + * The mapping shall fail if the buffer is allocated from vidmem. * * @kind [IN] * diff --git a/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.c b/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.c index 180a7858e..ee08035bd 100644 --- a/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.c +++ b/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -291,7 +291,7 @@ done: #define F_ATTRS_VALID 0x4ULL #define F_ATTRS_CACHEABLE 0x8ULL #define F_ATTRS_APERTURE_VIDMEM 0x10ULL -#define F_PLATFORM_ATOMIC 0x20ULL +#define F_SYSTEM_COHERENT 0x20ULL #define F_UPDATE_PTE 0x40ULL #define F_UPDATE_PTE_SPARSE 0x80ULL @@ -306,8 +306,8 @@ done: #define F_UPDATE_PTE_ATTRS_CACHEABLE 0x48ULL /* F_UPDATE_PTE | F_ATTRS_APERTURE_VIDMEM */ #define F_UPDATE_PTE_ATTRS_VIDMEM 0x50ULL -/* F_UPDATE_PTE | F_PLATFORM_ATOMIC */ -#define F_UPDATE_PTE_PLATFORM_ATOMIC 0x60ULL +/* F_UPDATE_PTE | F_SYSTEM_COHERENT */ +#define F_UPDATE_PTE_SYSTEM_COHERENT 0x60ULL static const char *f_gmmu_pte_locked[] = { [F_UPDATE_PTE_DEFAULT] = "update_pte_default", @@ -315,7 +315,7 @@ static const char *f_gmmu_pte_locked[] = { [F_UPDATE_PTE_ATTRS_VALID] = "update_pte_attrs_valid", [F_UPDATE_PTE_ATTRS_CACHEABLE] = "update_pte_attrs_cacheable", [F_UPDATE_PTE_ATTRS_VIDMEM] = "update_pte_attrs_vidmem", - [F_UPDATE_PTE_PLATFORM_ATOMIC] = "update_pte_platform_atomic", + [F_UPDATE_PTE_SYSTEM_COHERENT] = "update_pte_system_coherent", [F_UPDATE_PTE_SPARSE] = "update_pte_sparse", }; @@ -361,12 +361,15 @@ int test_update_gmmu_pte_locked(struct unit_module *m, vm.gmmu_page_sizes[GMMU_PAGE_SIZE_SMALL] = SZ_4K; paddr = branch & F_UPDATE_PTE ? size : 0ULL; - nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, - (branch & F_PLATFORM_ATOMIC ? true : false)); - attrs.platform_atomic = branch & F_PLATFORM_ATOMIC ? true : false; - attrs.aperture = branch & F_ATTRS_APERTURE_VIDMEM ? - APERTURE_VIDMEM : APERTURE_SYSMEM; + if (branch & F_ATTRS_APERTURE_VIDMEM) { + attrs.aperture = APERTURE_VIDMEM; + } else if (branch & F_SYSTEM_COHERENT) { + attrs.aperture = APERTURE_SYSMEM_COH; + } else { + attrs.aperture = APERTURE_SYSMEM; + } + attrs.priv = branch & F_ATTRS_PRIV ? true : false; attrs.rw_flag = branch & F_ATTRS_READ_ONLY ? gk20a_mem_flag_read_only : gk20a_mem_flag_none; @@ -386,9 +389,9 @@ int test_update_gmmu_pte_locked(struct unit_module *m, gmmu_new_pte_address_shift_v()) : gmmu_new_pte_address_sys_f(paddr >> gmmu_new_pte_address_shift_v()); - data |= branch & F_PLATFORM_ATOMIC ? - gmmu_new_pte_aperture_sys_mem_coh_f() : - branch & F_ATTRS_APERTURE_VIDMEM ? + data |= branch & F_SYSTEM_COHERENT ? + gmmu_new_pte_aperture_sys_mem_coh_f() : + branch & F_ATTRS_APERTURE_VIDMEM ? gmmu_new_pte_aperture_video_memory_f() : gmmu_new_pte_aperture_sys_mem_ncoh_f(); data |= branch & F_ATTRS_VALID ? gmmu_new_pte_valid_true_f() : @@ -539,7 +542,7 @@ struct unit_module_test mm_gmmu_gp10b_fusa_tests[] = { UNIT_TEST(update_gmmu_pte_locked_s3, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_ATTRS_VALID, 0), UNIT_TEST(update_gmmu_pte_locked_s4, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_ATTRS_CACHEABLE, 0), UNIT_TEST(update_gmmu_pte_locked_s5, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_ATTRS_VIDMEM, 0), - UNIT_TEST(update_gmmu_pte_locked_s6, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_PLATFORM_ATOMIC, 0), + UNIT_TEST(update_gmmu_pte_locked_s6, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_SYSTEM_COHERENT, 0), UNIT_TEST(update_gmmu_pte_locked_s7, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_SPARSE, 0), UNIT_TEST(gp10b_get_pde0_pgsz_s0, test_gp10b_get_pde0_pgsz, (void *)F_PDE_BIG_PAGE_APERTURE_SET_ONLY, 0), UNIT_TEST(gp10b_get_pde0_pgsz_s1, test_gp10b_get_pde0_pgsz, (void *)F_PDE_BIG_PAGE_APERTURE_ADDR_SET, 0), diff --git a/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.h b/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.h index 58e2ece3e..130f70551 100644 --- a/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.h +++ b/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -170,7 +170,7 @@ int test_update_gmmu_pde0_locked(struct unit_module *m, * Input: args (value can be F_UPDATE_PTE_PHYS_ADDR_ZERO, F_UPDATE_PTE_DEFAULT, * F_UPDATE_PTE_ATTRS_PRIV_READ_ONLY, F_UPDATE_PTE_ATTRS_VALID, * F_UPDATE_PTE_ATTRS_CACHEABLE, F_UPDATE_PTE_ATTRS_VIDMEM, - * F_UPDATE_PTE_PLATFORM_ATOMIC or F_UPDATE_PTE_SPARSE) + * F_UPDATE_PTE_SYSTEM_COHERENT or F_UPDATE_PTE_SPARSE) * * Steps: * - Update gmmu pte for given physical address.