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gpu: nvgpu: Remove gk20a support

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Remove gk20a support. Leave only gk20a code which is reused by other
GPUs.

JIRA NVGPU-38

Change-Id: I3d5f2bc9f71cd9f161e64436561a5eadd5786a3b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master/r/1507927
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Terje Bergstrom
2017-06-22 12:58:43 -07:00
committed by mobile promotions
parent 3ffcadc8dd
commit 82c0c96290
33 changed files with 9 additions and 2660 deletions
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4
drivers/gpu/nvgpu/Makefile.nvgpu
View File

@@ -89,9 +89,7 @@ nvgpu-y := \
gk20a/ltc_gk20a.o \
gk20a/fb_gk20a.o \
gk20a/hal.o \
gk20a/hal_gk20a.o \
gk20a/cde_gk20a.o \
gk20a/platform_gk20a_generic.o \
gk20a/tsg_gk20a.o \
gk20a/ctxsw_trace_gk20a.o \
gk20a/fecs_trace_gk20a.o \
@@ -153,8 +151,6 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
vgpu/tsg_vgpu.o \
vgpu/clk_vgpu.o \
vgpu/css_vgpu.o \
vgpu/gk20a/vgpu_hal_gk20a.o \
vgpu/gk20a/vgpu_gr_gk20a.o \
vgpu/gm20b/vgpu_hal_gm20b.o \
vgpu/gm20b/vgpu_gr_gm20b.o \
vgpu/sysfs_vgpu.o

19
drivers/gpu/nvgpu/common/linux/module.c
View File

@@ -234,8 +234,6 @@ done:
static struct of_device_id tegra_gk20a_of_match[] = {
#ifdef CONFIG_TEGRA_GK20A
{ .compatible = "nvidia,tegra124-gk20a",
.data = &gk20a_tegra_platform },
{ .compatible = "nvidia,tegra210-gm20b",
.data = &gm20b_tegra_platform },
#ifdef CONFIG_ARCH_TEGRA_18x_SOC
@@ -254,25 +252,8 @@ static struct of_device_id tegra_gk20a_of_match[] = {
{ .compatible = "nvidia,tegra124-gk20a-vgpu",
.data = &vgpu_tegra_platform },
#endif
#else
{ .compatible = "nvidia,tegra124-gk20a",
.data = &gk20a_generic_platform },
{ .compatible = "nvidia,tegra210-gm20b",
.data = &gk20a_generic_platform },
#ifdef CONFIG_ARCH_TEGRA_18x_SOC
{ .compatible = TEGRA_18x_GPU_COMPAT_TEGRA,
.data = &gk20a_generic_platform },
#endif
#endif
{ .compatible = "nvidia,generic-gk20a",
.data = &gk20a_generic_platform },
{ .compatible = "nvidia,generic-gm20b",
.data = &gk20a_generic_platform },
#ifdef CONFIG_ARCH_TEGRA_18x_SOC
{ .compatible = "nvidia,generic-gp10b",
.data = &gk20a_generic_platform },
#endif
{ },
};

135
drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c
View File

@@ -47,7 +47,6 @@
#include <nvgpu/linux/dma.h>
#include "gk20a/gk20a.h"
#include "gk20a/hal_gk20a.h"
#include "gk20a/platform_gk20a.h"
#include "gk20a/gk20a_scale.h"
#include "gm20b/clk_gm20b.h"
@@ -231,66 +230,6 @@ static unsigned long gk20a_tegra_get_emc_rate(struct gk20a *g,
return MHZ_TO_HZ(emc_rate);
}
/*
* gk20a_tegra_postscale(profile, freq)
*
* This function sets emc frequency based on current gpu frequency
*/
static void gk20a_tegra_postscale(struct device *dev,
unsigned long freq)
{
struct gk20a_platform *platform = dev_get_drvdata(dev);
struct gk20a_scale_profile *profile = platform->g->scale_profile;
struct gk20a_emc_params *emc_params = profile->private_data;
struct gk20a *g = get_gk20a(dev);
struct clk *emc_clk = platform->clk[2];
enum tegra_chipid chip_id = tegra_get_chip_id();
unsigned long emc_target;
unsigned long emc_freq_lower, emc_freq_upper, emc_freq_rounded;
emc_target = gk20a_tegra_get_emc_rate(g, emc_params);
switch (chip_id) {
case TEGRA124:
case TEGRA132:
/* T124 and T132 don't apply any rounding. The resulting
* emc frequency gets implicitly rounded up after issuing
* the clock_set_request.
* So explicitly round up the emc target here to achieve
* the same outcome. */
emc_freq_rounded =
tegra_emc_round_rate_updown(emc_target, true);
break;
case TEGRA210:
emc_freq_lower = (unsigned long)
tegra_emc_round_rate_updown(emc_target, false);
emc_freq_upper = (unsigned long)
tegra_emc_round_rate_updown(emc_target, true);
/* round to the nearest frequency step */
if (emc_target < (emc_freq_lower + emc_freq_upper) / 2)
emc_freq_rounded = emc_freq_lower;
else
emc_freq_rounded = emc_freq_upper;
break;
default:
/* a proper rounding function needs to be implemented
* for emc in t18x */
emc_freq_rounded = clk_round_rate(emc_clk, emc_target);
break;
}
/* only change the emc clock if new rounded frequency is different
* from previously set emc rate */
if (emc_freq_rounded != emc_params->freq_last_set) {
clk_set_rate(emc_clk, emc_freq_rounded);
emc_params->freq_last_set = emc_freq_rounded;
}
}
/*
* gk20a_tegra_prescale(profile, freq)
*
@@ -619,30 +558,6 @@ err_get_clock:
return ret;
}
static int gk20a_tegra_reset_assert(struct device *dev)
{
struct gk20a_platform *platform = gk20a_get_platform(dev);
if (!platform->clk_reset)
platform->clk_reset = platform->clk[0];
tegra_periph_reset_assert(platform->clk_reset);
return 0;
}
static int gk20a_tegra_reset_deassert(struct device *dev)
{
struct gk20a_platform *platform = gk20a_get_platform(dev);
if (!platform->clk_reset)
return -EINVAL;
tegra_periph_reset_deassert(platform->clk_reset);
return 0;
}
#if defined(CONFIG_RESET_CONTROLLER) && defined(CONFIG_COMMON_CLK)
static int gm20b_tegra_reset_assert(struct device *dev)
{
@@ -992,54 +907,6 @@ static int gk20a_clk_get_freqs(struct device *dev,
}
#endif
struct gk20a_platform gk20a_tegra_platform = {
.has_syncpoints = true,
.aggressive_sync_destroy_thresh = 64,
/* power management configuration */
.railgate_delay_init = 500,
.can_railgate_init = true,
.can_elpg_init = true,
.enable_slcg = true,
.enable_blcg = true,
.enable_elcg = true,
.enable_elpg = true,
.enable_aelpg = true,
.ptimer_src_freq = 12000000,
.force_reset_in_do_idle = false,
.default_big_page_size = SZ_128K,
.ch_wdt_timeout_ms = 7000,
.probe = gk20a_tegra_probe,
.late_probe = gk20a_tegra_late_probe,
.remove = gk20a_tegra_remove,
/* power management callbacks */
.suspend = gk20a_tegra_suspend,
.busy = gk20a_tegra_busy,
.idle = gk20a_tegra_idle,
.reset_assert = gk20a_tegra_reset_assert,
.reset_deassert = gk20a_tegra_reset_deassert,
/* frequency scaling configuration */
.prescale = gk20a_tegra_prescale,
.postscale = gk20a_tegra_postscale,
.devfreq_governor = "nvhost_podgov",
.qos_notify = gk20a_scale_qos_notify,
.dump_platform_dependencies = gk20a_tegra_debug_dump,
.soc_name = "tegra12x",
.unified_memory = true,
};
struct gk20a_platform gm20b_tegra_platform = {
.has_syncpoints = true,
.aggressive_sync_destroy_thresh = 64,
@@ -1097,8 +964,6 @@ struct gk20a_platform gm20b_tegra_platform = {
.prescale = gk20a_tegra_prescale,
#ifdef CONFIG_TEGRA_BWMGR
.postscale = gm20b_tegra_postscale,
#else
.postscale = gk20a_tegra_postscale,
#endif
.devfreq_governor = "nvhost_podgov",
.qos_notify = gk20a_scale_qos_notify,

61
drivers/gpu/nvgpu/gk20a/fb_gk20a.c
View File

@@ -50,53 +50,6 @@ void gk20a_fb_init_hw(struct gk20a *g)
gk20a_writel(g, fb_niso_flush_sysmem_addr_r(), addr);
}
static void gk20a_fb_set_mmu_page_size(struct gk20a *g)
{
/* set large page size in fb */
u32 fb_mmu_ctrl = gk20a_readl(g, fb_mmu_ctrl_r());
fb_mmu_ctrl = (fb_mmu_ctrl &
~fb_mmu_ctrl_vm_pg_size_f(~0x0)) |
fb_mmu_ctrl_vm_pg_size_128kb_f();
gk20a_writel(g, fb_mmu_ctrl_r(), fb_mmu_ctrl);
}
static unsigned int gk20a_fb_compression_page_size(struct gk20a *g)
{
return SZ_128K;
}
static unsigned int gk20a_fb_compressible_page_size(struct gk20a *g)
{
return SZ_64K;
}
static bool gk20a_fb_debug_mode_enabled(struct gk20a *g)
{
u32 debug_ctrl = gk20a_readl(g, fb_mmu_debug_ctrl_r());
return fb_mmu_debug_ctrl_debug_v(debug_ctrl) ==
fb_mmu_debug_ctrl_debug_enabled_v();
}
static void gk20a_fb_set_debug_mode(struct gk20a *g, bool enable)
{
u32 reg_val, debug_ctrl;
reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r());
if (enable) {
debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f();
g->mmu_debug_ctrl = true;
} else {
debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f();
g->mmu_debug_ctrl = false;
}
reg_val = set_field(reg_val,
fb_mmu_debug_ctrl_debug_m(), debug_ctrl);
gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val);
}
void gk20a_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb)
{
struct nvgpu_timeout timeout;
@@ -159,17 +112,3 @@ void gk20a_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb)
out:
nvgpu_mutex_release(&g->mm.tlb_lock);
}
void gk20a_init_fb(struct gpu_ops *gops)
{
gops->fb.init_hw = gk20a_fb_init_hw;
gops->fb.reset = fb_gk20a_reset;
gops->fb.set_mmu_page_size = gk20a_fb_set_mmu_page_size;
gops->fb.compression_page_size = gk20a_fb_compression_page_size;
gops->fb.compressible_page_size = gk20a_fb_compressible_page_size;
gops->fb.is_debug_mode_enabled = gk20a_fb_debug_mode_enabled;
gops->fb.set_debug_mode = gk20a_fb_set_debug_mode;
gops->fb.tlb_invalidate = gk20a_fb_tlb_invalidate;
gk20a_init_uncompressed_kind_map();
gk20a_init_kind_attr();
}

3
drivers/gpu/nvgpu/gk20a/fb_gk20a.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -17,7 +17,6 @@
struct gk20a;
struct nvgpu_mem;
void gk20a_init_fb(struct gpu_ops *gops);
void fb_gk20a_reset(struct gk20a *g);
void gk20a_fb_init_hw(struct gk20a *g);
void gk20a_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb);

195
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -822,51 +822,6 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
return 0;
}
static void gk20a_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
{
/*
* These are all errors which indicate something really wrong
* going on in the device
*/
f->intr.pbdma.device_fatal_0 =
pbdma_intr_0_memreq_pending_f() |
pbdma_intr_0_memack_timeout_pending_f() |
pbdma_intr_0_memack_extra_pending_f() |
pbdma_intr_0_memdat_timeout_pending_f() |
pbdma_intr_0_memdat_extra_pending_f() |
pbdma_intr_0_memflush_pending_f() |
pbdma_intr_0_memop_pending_f() |
pbdma_intr_0_lbconnect_pending_f() |
pbdma_intr_0_lback_timeout_pending_f() |
pbdma_intr_0_lback_extra_pending_f() |
pbdma_intr_0_lbdat_timeout_pending_f() |
pbdma_intr_0_lbdat_extra_pending_f() |
pbdma_intr_0_xbarconnect_pending_f() |
pbdma_intr_0_pri_pending_f();
/*
* These are data parsing, framing errors or others which can be
* recovered from with intervention... or just resetting the
* channel
*/
f->intr.pbdma.channel_fatal_0 =
pbdma_intr_0_gpfifo_pending_f() |
pbdma_intr_0_gpptr_pending_f() |
pbdma_intr_0_gpentry_pending_f() |
pbdma_intr_0_gpcrc_pending_f() |
pbdma_intr_0_pbptr_pending_f() |
pbdma_intr_0_pbentry_pending_f() |
pbdma_intr_0_pbcrc_pending_f() |
pbdma_intr_0_method_pending_f() |
pbdma_intr_0_methodcrc_pending_f() |
pbdma_intr_0_pbseg_pending_f() |
pbdma_intr_0_signature_pending_f();
/* Can be used for sw-methods, or represents a recoverable timeout. */
f->intr.pbdma.restartable_0 =
pbdma_intr_0_device_pending_f();
}
static int gk20a_init_fifo_setup_sw(struct gk20a *g)
{
struct fifo_gk20a *f = &g->fifo;
@@ -1722,46 +1677,6 @@ static void gk20a_fifo_get_faulty_id_type(struct gk20a *g, int engine_id,
fifo_engine_status_id_type_v(status);
}
static void gk20a_fifo_trigger_mmu_fault(struct gk20a *g,
unsigned long engine_ids)
{
struct nvgpu_timeout timeout;
unsigned long delay = GR_IDLE_CHECK_DEFAULT;
unsigned long engine_id;
/* trigger faults for all bad engines */
for_each_set_bit(engine_id, &engine_ids, 32) {
u32 mmu_id;
if (!gk20a_fifo_is_valid_engine_id(g, engine_id)) {
WARN_ON(true);
break;
}
mmu_id = gk20a_engine_id_to_mmu_id(g, engine_id);
if (mmu_id != FIFO_INVAL_ENGINE_ID)
gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id),
fifo_trigger_mmu_fault_id_f(mmu_id) |
fifo_trigger_mmu_fault_enable_f(1));
}
/* Wait for MMU fault to trigger */
nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
NVGPU_TIMER_CPU_TIMER);
do {
if (gk20a_readl(g, fifo_intr_0_r()) &
fifo_intr_0_mmu_fault_pending_f())
break;
nvgpu_usleep_range(delay, delay * 2);
delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX);
} while (!nvgpu_timeout_expired_msg(&timeout, "mmu fault timeout"));
/* release mmu fault trigger */
for_each_set_bit(engine_id, &engine_ids, 32)
gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id), 0);
}
static u32 gk20a_fifo_engines_on_id(struct gk20a *g, u32 id, bool is_tsg)
{
unsigned int i;
@@ -3406,22 +3321,6 @@ int gk20a_fifo_wait_engine_idle(struct gk20a *g)
return ret;
}
static void gk20a_fifo_apply_pb_timeout(struct gk20a *g)
{
u32 timeout;
if (nvgpu_platform_is_silicon(g)) {
timeout = gk20a_readl(g, fifo_pb_timeout_r());
timeout &= ~fifo_pb_timeout_detection_enabled_f();
gk20a_writel(g, fifo_pb_timeout_r(), timeout);
}
}
static u32 gk20a_fifo_get_num_fifos(struct gk20a *g)
{
return ccsr_channel__size_1_v();
}
u32 gk20a_fifo_get_pbdma_signature(struct gk20a *g)
{
return pbdma_signature_hw_valid_f() | pbdma_signature_sw_zero_f();
@@ -3686,38 +3585,6 @@ void gk20a_fifo_disable_channel(struct channel_gk20a *ch)
ccsr_channel_enable_clr_true_f());
}
static void gk20a_fifo_channel_bind(struct channel_gk20a *c)
{
struct gk20a *g = c->g;
u32 inst_ptr = gk20a_mm_inst_block_addr(g, &c->inst_block) >>
ram_in_base_shift_v();
gk20a_dbg_info("bind channel %d inst ptr 0x%08x",
c->chid, inst_ptr);
gk20a_writel(g, ccsr_channel_r(c->chid),
(gk20a_readl(g, ccsr_channel_r(c->chid)) &
~ccsr_channel_runlist_f(~0)) |
ccsr_channel_runlist_f(c->runlist_id));
gk20a_writel(g, ccsr_channel_inst_r(c->chid),
ccsr_channel_inst_ptr_f(inst_ptr) |
nvgpu_aperture_mask(g, &c->inst_block,
ccsr_channel_inst_target_sys_mem_ncoh_f(),
ccsr_channel_inst_target_vid_mem_f()) |
ccsr_channel_inst_bind_true_f());
gk20a_writel(g, ccsr_channel_r(c->chid),
(gk20a_readl(g, ccsr_channel_r(c->chid)) &
~ccsr_channel_enable_set_f(~0)) |
ccsr_channel_enable_set_true_f());
wmb();
atomic_set(&c->bound, true);
}
void gk20a_fifo_channel_unbind(struct channel_gk20a *ch_gk20a)
{
struct gk20a *g = ch_gk20a->g;
@@ -4080,65 +3947,3 @@ int gk20a_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
return 0;
}
#endif
void gk20a_init_fifo(struct gpu_ops *gops)
{
gops->fifo.disable_channel = gk20a_fifo_disable_channel;
gops->fifo.enable_channel = gk20a_fifo_enable_channel;
gops->fifo.bind_channel = gk20a_fifo_channel_bind;
gops->fifo.unbind_channel = gk20a_fifo_channel_unbind;
gops->fifo.init_fifo_setup_hw = gk20a_init_fifo_setup_hw;
gops->fifo.preempt_channel = gk20a_fifo_preempt_channel;
gops->fifo.preempt_tsg = gk20a_fifo_preempt_tsg;
gops->fifo.update_runlist = gk20a_fifo_update_runlist;
gops->fifo.trigger_mmu_fault = gk20a_fifo_trigger_mmu_fault;
gops->fifo.get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info;
gops->fifo.apply_pb_timeout = gk20a_fifo_apply_pb_timeout;
gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle;
gops->fifo.get_num_fifos = gk20a_fifo_get_num_fifos;
gops->fifo.get_pbdma_signature = gk20a_fifo_get_pbdma_signature;
gops->fifo.set_runlist_interleave = gk20a_fifo_set_runlist_interleave;
gops->fifo.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice;
gops->fifo.force_reset_ch = gk20a_fifo_force_reset_ch;
gops->fifo.engine_enum_from_type = gk20a_fifo_engine_enum_from_type;
/* gk20a doesn't support device_info_data packet parsing */
gops->fifo.device_info_data_parse = NULL;
gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
gops->fifo.init_engine_info = gk20a_fifo_init_engine_info;
gops->fifo.runlist_entry_size = ram_rl_entry_size_v;
gops->fifo.get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry;
gops->fifo.get_ch_runlist_entry = gk20a_get_ch_runlist_entry;
gops->fifo.is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc;
gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status;
gops->fifo.dump_eng_status = gk20a_dump_eng_status;
gops->fifo.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc;
gops->fifo.intr_0_error_mask = gk20a_fifo_intr_0_error_mask;
gops->fifo.is_preempt_pending = gk20a_fifo_is_preempt_pending;
gops->fifo.init_pbdma_intr_descs = gk20a_fifo_init_pbdma_intr_descs;
gops->fifo.reset_enable_hw = gk20a_init_fifo_reset_enable_hw;
gops->fifo.setup_ramfc = gk20a_fifo_setup_ramfc;
gops->fifo.channel_set_priority = gk20a_fifo_set_priority;
gops->fifo.channel_set_timeslice = gk20a_fifo_set_timeslice;
gops->fifo.alloc_inst = gk20a_fifo_alloc_inst;
gops->fifo.free_inst = gk20a_fifo_free_inst;
gops->fifo.setup_userd = gk20a_fifo_setup_userd;
gops->fifo.userd_gp_get = gk20a_fifo_userd_gp_get;
gops->fifo.userd_gp_put = gk20a_fifo_userd_gp_put;
gops->fifo.userd_pb_get = gk20a_fifo_userd_pb_get;
gops->fifo.pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val;
gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg;
gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error;
gops->fifo.handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0;
gops->fifo.handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1;
#ifdef CONFIG_TEGRA_GK20A_NVHOST
gops->fifo.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf;
gops->fifo.free_syncpt_buf = gk20a_fifo_free_syncpt_buf;
gops->fifo.add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd;
gops->fifo.get_syncpt_wait_cmd_size =
gk20a_fifo_get_syncpt_wait_cmd_size;
gops->fifo.add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd;
gops->fifo.get_syncpt_incr_cmd_size =
gk20a_fifo_get_syncpt_incr_cmd_size;
#endif
}

1
drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
View File

@@ -268,7 +268,6 @@ int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch,
u32 err_code, bool verbose);
void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id);
int gk20a_init_fifo_reset_enable_hw(struct gk20a *g);
void gk20a_init_fifo(struct gpu_ops *gops);
void fifo_gk20a_finish_mmu_fault_handling(struct gk20a *g,
unsigned long fault_id);

51
drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c
View File

@@ -66,50 +66,6 @@ static int gr_gk20a_alloc_load_netlist_aiv(struct gk20a *g, u32 *src, u32 len,
return 0;
}
static int gr_gk20a_get_netlist_name(struct gk20a *g, int index, char *name)
{
switch (index) {
#ifdef GK20A_NETLIST_IMAGE_FW_NAME
case NETLIST_FINAL:
sprintf(name, GK20A_NETLIST_IMAGE_FW_NAME);
return 0;
#endif
#ifdef GK20A_NETLIST_IMAGE_A
case NETLIST_SLOT_A:
sprintf(name, GK20A_NETLIST_IMAGE_A);
return 0;
#endif
#ifdef GK20A_NETLIST_IMAGE_B
case NETLIST_SLOT_B:
sprintf(name, GK20A_NETLIST_IMAGE_B);
return 0;
#endif
#ifdef GK20A_NETLIST_IMAGE_C
case NETLIST_SLOT_C:
sprintf(name, GK20A_NETLIST_IMAGE_C);
return 0;
#endif
#ifdef GK20A_NETLIST_IMAGE_D
case NETLIST_SLOT_D:
sprintf(name, GK20A_NETLIST_IMAGE_D);
return 0;
#endif
default:
return -1;
}
return -1;
}
static bool gr_gk20a_is_firmware_defined(void)
{
#ifdef GK20A_NETLIST_IMAGE_FW_NAME
return true;
#else
return false;
#endif
}
static int gr_gk20a_init_ctx_vars_fw(struct gk20a *g, struct gr_gk20a *gr)
{
struct nvgpu_firmware *netlist_fw;
@@ -448,10 +404,3 @@ int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr)
else
return gr_gk20a_init_ctx_vars_fw(g, gr);
}
void gk20a_init_gr_ctx(struct gpu_ops *gops)
{
gops->gr_ctx.get_netlist_name = gr_gk20a_get_netlist_name;
gops->gr_ctx.is_fw_defined = gr_gk20a_is_firmware_defined;
gops->gr_ctx.use_dma_for_fw_bootstrap = true;
}

4
drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h
View File

@@ -22,10 +22,6 @@
struct gr_gk20a;
/* production netlist, one and only one from below */
/*#undef GK20A_NETLIST_IMAGE_FW_NAME*/
#define GK20A_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_B
/* emulation netlists, match majorV with HW */
#define GK20A_NETLIST_IMAGE_A "NETA_img.bin"
#define GK20A_NETLIST_IMAGE_B "NETB_img.bin"

1167
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

File diff suppressed because it is too large Load Diff

1
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -484,7 +484,6 @@ struct gpu_ops;
int gr_gk20a_load_golden_ctx_image(struct gk20a *g,
struct channel_gk20a *c);
void gk20a_init_gr(struct gk20a *g);
void gk20a_init_gr_ops(struct gpu_ops *gops);
int gk20a_init_gr_support(struct gk20a *g);
int gk20a_enable_gr_hw(struct gk20a *g);
int gk20a_gr_reset(struct gk20a *g);

5
drivers/gpu/nvgpu/gk20a/hal.c
View File

@@ -14,7 +14,6 @@
*/
#include "gk20a.h"
#include "hal_gk20a.h"
#include "hal.h"
#include "gm20b/hal_gm20b.h"
#include "gp10b/hal_gp10b.h"
@@ -30,10 +29,6 @@ int gpu_init_hal(struct gk20a *g)
{
u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl;
switch (ver) {
case GK20A_GPUID_GK20A:
gk20a_dbg_info("gk20a detected");
gk20a_init_hal(g);
break;
case GK20A_GPUID_GM20B:
case GK20A_GPUID_GM20B_B:
gk20a_dbg_info("gm20b detected");

208
drivers/gpu/nvgpu/gk20a/hal_gk20a.c
View File

@@ -1,208 +0,0 @@
/*
* drivers/video/tegra/host/gk20a/hal_gk20a.c
*
* GK20A Tegra HAL interface.
*
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "hal_gk20a.h"
#include "bus_gk20a.h"
#include "ltc_gk20a.h"
#include "fb_gk20a.h"
#include "gk20a.h"
#include "gk20a_gating_reglist.h"
#include "channel_gk20a.h"
#include "gr_ctx_gk20a.h"
#include "fecs_trace_gk20a.h"
#include "mm_gk20a.h"
#include "mc_gk20a.h"
#include "flcn_gk20a.h"
#include "pmu_gk20a.h"
#include "clk_gk20a.h"
#include "regops_gk20a.h"
#include "therm_gk20a.h"
#include "tsg_gk20a.h"
#include "dbg_gpu_gk20a.h"
#include "css_gr_gk20a.h"
#include "pramin_gk20a.h"
#include "priv_ring_gk20a.h"
#include <nvgpu/debug.h>
#include <nvgpu/log.h>
#include <nvgpu/bug.h>
#include <nvgpu/hw/gk20a/hw_proj_gk20a.h>
static const struct gpu_ops gk20a_ops = {
.ltc = {
.determine_L2_size_bytes = gk20a_determine_L2_size_bytes,
.init_comptags = gk20a_ltc_init_comptags,
.cbc_ctrl = gk20a_ltc_cbc_ctrl,
.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry,
.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry,
.init_cbc = gk20a_ltc_init_cbc,
#ifdef CONFIG_DEBUG_FS
.sync_debugfs = gk20a_ltc_sync_debugfs,
#endif
.init_fs_state = gk20a_ltc_init_fs_state,
.isr = gk20a_ltc_isr,
},
.clock_gating = {
.slcg_gr_load_gating_prod =
gr_gk20a_slcg_gr_load_gating_prod,
.slcg_perf_load_gating_prod =
gr_gk20a_slcg_perf_load_gating_prod,
.slcg_ltc_load_gating_prod =
ltc_gk20a_slcg_ltc_load_gating_prod,
.blcg_gr_load_gating_prod =
gr_gk20a_blcg_gr_load_gating_prod,
.pg_gr_load_gating_prod =
gr_gk20a_pg_gr_load_gating_prod,
.slcg_therm_load_gating_prod =
gr_gk20a_slcg_therm_load_gating_prod,
},
};
static int gk20a_get_litter_value(struct gk20a *g, int value)
{
int ret = EINVAL;
switch (value) {
case GPU_LIT_NUM_GPCS:
ret = proj_scal_litter_num_gpcs_v();
break;
case GPU_LIT_NUM_PES_PER_GPC:
ret = proj_scal_litter_num_pes_per_gpc_v();
break;
case GPU_LIT_NUM_ZCULL_BANKS:
ret = proj_scal_litter_num_zcull_banks_v();
break;
case GPU_LIT_NUM_TPC_PER_GPC:
ret = proj_scal_litter_num_tpc_per_gpc_v();
break;
case GPU_LIT_NUM_SM_PER_TPC:
ret = 1;
break;
case GPU_LIT_NUM_FBPS:
ret = proj_scal_litter_num_fbps_v();
break;
case GPU_LIT_GPC_BASE:
ret = proj_gpc_base_v();
break;
case GPU_LIT_GPC_STRIDE:
ret = proj_gpc_stride_v();
break;
case GPU_LIT_GPC_SHARED_BASE:
ret = proj_gpc_shared_base_v();
break;
case GPU_LIT_TPC_IN_GPC_BASE:
ret = proj_tpc_in_gpc_base_v();
break;
case GPU_LIT_TPC_IN_GPC_STRIDE:
ret = proj_tpc_in_gpc_stride_v();
break;
case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
ret = proj_tpc_in_gpc_shared_base_v();
break;
case GPU_LIT_PPC_IN_GPC_BASE:
ret = proj_ppc_in_gpc_base_v();
break;
case GPU_LIT_PPC_IN_GPC_STRIDE:
ret = proj_ppc_in_gpc_stride_v();
break;
case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
ret = proj_ppc_in_gpc_shared_base_v();
break;
case GPU_LIT_ROP_BASE:
ret = proj_rop_base_v();
break;
case GPU_LIT_ROP_STRIDE:
ret = proj_rop_stride_v();
break;
case GPU_LIT_ROP_SHARED_BASE:
ret = proj_rop_shared_base_v();
break;
case GPU_LIT_HOST_NUM_ENGINES:
ret = proj_host_num_engines_v();
break;
case GPU_LIT_HOST_NUM_PBDMA:
ret = proj_host_num_pbdma_v();
break;
case GPU_LIT_LTC_STRIDE:
ret = proj_ltc_stride_v();
break;
case GPU_LIT_LTS_STRIDE:
ret = proj_lts_stride_v();
break;
/* GK20A does not have a FBPA unit, despite what's listed in the
* hw headers or read back through NV_PTOP_SCAL_NUM_FBPAS,
* so hardcode all values to 0.
*/
case GPU_LIT_NUM_FBPAS:
case GPU_LIT_FBPA_STRIDE:
case GPU_LIT_FBPA_BASE:
case GPU_LIT_FBPA_SHARED_BASE:
ret = 0;
break;
default:
nvgpu_err(g, "Missing definition %d", value);
BUG();
break;
}
return ret;
}
int gk20a_init_hal(struct gk20a *g)
{
struct gpu_ops *gops = &g->ops;
struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
gops->ltc = gk20a_ops.ltc;
gops->clock_gating = gk20a_ops.clock_gating;
gops->privsecurity = 0;
gops->securegpccs = 0;
gops->pmupstate = false;
gk20a_init_bus(gops);
gk20a_init_mc(gops);
gk20a_init_priv_ring(gops);
gk20a_init_gr_ops(gops);
gk20a_init_fecs_trace_ops(gops);
gk20a_init_fb(gops);
gk20a_init_fifo(gops);
gk20a_init_ce2(gops);
gk20a_init_gr_ctx(gops);
gk20a_init_mm(gops);
gk20a_falcon_init_hal(gops);
gk20a_init_pmu_ops(gops);
gk20a_init_regops(gops);
gk20a_init_debug_ops(gops);
gk20a_init_dbg_session_ops(gops);
gk20a_init_therm_ops(gops);
gk20a_init_tsg_ops(gops);
gk20a_init_pramin_ops(gops);
#if defined(CONFIG_GK20A_CYCLE_STATS)
gk20a_init_css_ops(gops);
#endif
g->name = "gk20a";
gops->chip_init_gpu_characteristics = gk20a_init_gpu_characteristics;
gops->get_litter_value = gk20a_get_litter_value;
c->twod_class = FERMI_TWOD_A;
c->threed_class = KEPLER_C;
c->compute_class = KEPLER_COMPUTE_A;
c->gpfifo_class = KEPLER_CHANNEL_GPFIFO_C;
c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_A;
c->dma_copy_class = KEPLER_DMA_COPY_A;
return 0;
}

25
drivers/gpu/nvgpu/gk20a/hal_gk20a.h
View File

@@ -1,25 +0,0 @@
/*
* drivers/video/tegra/host/gk20a/hal_gk20a.h
*
* GK20A Hardware Abstraction Layer functions definitions.
*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __HAL_GK20A__
#define __HAL_GK20A__
struct gk20a;
int gk20a_init_hal(struct gk20a *g);
#endif /* __HAL_GK20A__ */

323
drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
View File

@@ -16,19 +16,10 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <trace/events/gk20a.h>
#include <nvgpu/timers.h>
#include <nvgpu/log.h>
#include <nvgpu/bug.h>
#include <nvgpu/enabled.h>
#include <nvgpu/dma.h>
#include "gk20a.h"
#include "gr_gk20a.h"
#include "ltc_gk20a.h"
#include <nvgpu/hw/gk20a/hw_ltc_gk20a.h>
/* Non HW reg dependent stuff: */
@@ -49,317 +40,3 @@ int gk20a_ltc_alloc_virt_cbc(struct gk20a *g, size_t compbit_backing_size)
compbit_backing_size,
&gr->compbit_store.mem);
}
/* HW reg dependent stuff: */
int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
{
/* max memory size (MB) to cover */
u32 max_size = gr->max_comptag_mem;
/* one tag line covers 128KB */
u32 max_comptag_lines = max_size << 3;
u32 hw_max_comptag_lines =
ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v();
u32 cbc_param =
gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r());
u32 comptags_per_cacheline =
ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(cbc_param);
u32 slices_per_fbp =
ltc_ltcs_ltss_cbc_param_slices_per_fbp_v(cbc_param);
u32 cacheline_size =
512 << ltc_ltcs_ltss_cbc_param_cache_line_size_v(cbc_param);
u32 compbit_backing_size;
int err;
gk20a_dbg_fn("");
if (max_comptag_lines == 0)
return 0;
if (max_comptag_lines > hw_max_comptag_lines)
max_comptag_lines = hw_max_comptag_lines;
/* no hybird fb */
compbit_backing_size =
DIV_ROUND_UP(max_comptag_lines, comptags_per_cacheline) *
cacheline_size * slices_per_fbp * gr->num_fbps;
/* aligned to 2KB * num_fbps */
compbit_backing_size +=
gr->num_fbps << ltc_ltcs_ltss_cbc_base_alignment_shift_v();
/* must be a multiple of 64KB */
compbit_backing_size = roundup(compbit_backing_size, 64*1024);
max_comptag_lines =
(compbit_backing_size * comptags_per_cacheline) /
cacheline_size * slices_per_fbp * gr->num_fbps;
if (max_comptag_lines > hw_max_comptag_lines)
max_comptag_lines = hw_max_comptag_lines;
gk20a_dbg_info("compbit backing store size : %d",
compbit_backing_size);
gk20a_dbg_info("max comptag lines : %d",
max_comptag_lines);
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size);
else
err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size);
if (err)
return err;
err = gk20a_comptag_allocator_init(&gr->comp_tags, max_comptag_lines);
if (err)
return err;
gr->comptags_per_cacheline = comptags_per_cacheline;
gr->slices_per_ltc = slices_per_fbp / g->ltc_count;
gr->cacheline_size = cacheline_size;
return 0;
}
int gk20a_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op,
u32 min, u32 max)
{
int err = 0;
struct gr_gk20a *gr = &g->gr;
u32 fbp, slice, ctrl1, val, hw_op = 0;
u32 slices_per_fbp =
ltc_ltcs_ltss_cbc_param_slices_per_fbp_v(
gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r()));
u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
gk20a_dbg_fn("");
trace_gk20a_ltc_cbc_ctrl_start(g->name, op, min, max);
if (gr->compbit_store.mem.size == 0)
return 0;
nvgpu_mutex_acquire(&g->mm.l2_op_lock);
if (op == gk20a_cbc_op_clear) {
gk20a_writel(g, ltc_ltcs_ltss_cbc_ctrl2_r(),
ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(min));
gk20a_writel(g, ltc_ltcs_ltss_cbc_ctrl3_r(),
ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(max));
hw_op = ltc_ltcs_ltss_cbc_ctrl1_clear_active_f();
} else if (op == gk20a_cbc_op_clean) {
hw_op = ltc_ltcs_ltss_cbc_ctrl1_clean_active_f();
} else if (op == gk20a_cbc_op_invalidate) {
hw_op = ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f();
} else {
BUG_ON(1);
}
gk20a_writel(g, ltc_ltcs_ltss_cbc_ctrl1_r(),
gk20a_readl(g, ltc_ltcs_ltss_cbc_ctrl1_r()) | hw_op);
for (fbp = 0; fbp < gr->num_fbps; fbp++) {
struct nvgpu_timeout timeout;
nvgpu_timeout_init(g, &timeout, 200, NVGPU_TIMER_RETRY_TIMER);
for (slice = 0; slice < slices_per_fbp; slice++) {
ctrl1 = ltc_ltc0_lts0_cbc_ctrl1_r() +
fbp * ltc_stride +
slice * lts_stride;
do {
val = gk20a_readl(g, ctrl1);
if (!(val & hw_op))
break;
nvgpu_udelay(5);
} while (!nvgpu_timeout_expired(&timeout));
if (nvgpu_timeout_peek_expired(&timeout)) {
nvgpu_err(g, "comp tag clear timeout");
err = -EBUSY;
goto out;
}
}
}
out:
trace_gk20a_ltc_cbc_ctrl_done(g->name);
nvgpu_mutex_release(&g->mm.l2_op_lock);
return err;
}
void gk20a_ltc_init_fs_state(struct gk20a *g)
{
gk20a_dbg_info("initialize gk20a L2");
g->max_ltc_count = g->ltc_count = 1;
}
void gk20a_ltc_isr(struct gk20a *g)
{
u32 intr;
intr = gk20a_readl(g, ltc_ltc0_ltss_intr_r());
nvgpu_err(g, "ltc: %08x", intr);
gk20a_writel(g, ltc_ltc0_ltss_intr_r(), intr);
}
int gk20a_determine_L2_size_bytes(struct gk20a *g)
{
u32 lts_per_ltc;
u32 ways;
u32 sets;
u32 bytes_per_line;
u32 active_ltcs;
u32 cache_size;
u32 tmp;
u32 active_sets_value;
tmp = gk20a_readl(g, ltc_ltc0_lts0_tstg_cfg1_r());
ways = hweight32(ltc_ltc0_lts0_tstg_cfg1_active_ways_v(tmp));
active_sets_value = ltc_ltc0_lts0_tstg_cfg1_active_sets_v(tmp);
if (active_sets_value == ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v()) {
sets = 64;
} else if (active_sets_value ==
ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v()) {
sets = 32;
} else if (active_sets_value ==
ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v()) {
sets = 16;
} else {
nvgpu_err(g,
"Unknown constant %u for active sets",
(unsigned)active_sets_value);
sets = 0;
}
active_ltcs = g->gr.num_fbps;
/* chip-specific values */
lts_per_ltc = 1;
bytes_per_line = 128;
cache_size = active_ltcs * lts_per_ltc * ways * sets * bytes_per_line;
return cache_size;
}
/*
* Sets the ZBC color for the passed index.
*/
void gk20a_ltc_set_zbc_color_entry(struct gk20a *g,
struct zbc_entry *color_val,
u32 index)
{
u32 i;
u32 real_index = index + GK20A_STARTOF_ZBC_TABLE;
gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index));
for (i = 0;
i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) {
gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i),
color_val->color_l2[i]);
}
gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r());
}
/*
* Sets the ZBC depth for the passed index.
*/
void gk20a_ltc_set_zbc_depth_entry(struct gk20a *g,
struct zbc_entry *depth_val,
u32 index)
{
u32 real_index = index + GK20A_STARTOF_ZBC_TABLE;
gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index));
gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(),
depth_val->depth);
gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r());
}
void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
{
u32 max_size = gr->max_comptag_mem;
u32 max_comptag_lines = max_size << 3;
u32 compbit_base_post_divide;
u64 compbit_base_post_multiply64;
u64 compbit_store_iova;
u64 compbit_base_post_divide64;
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem);
else
compbit_store_iova = g->ops.mm.get_iova_addr(g,
gr->compbit_store.mem.priv.sgt->sgl, 0);
compbit_base_post_divide64 = compbit_store_iova >>
ltc_ltcs_ltss_cbc_base_alignment_shift_v();
do_div(compbit_base_post_divide64, g->ltc_count);
compbit_base_post_divide = u64_lo32(compbit_base_post_divide64);
compbit_base_post_multiply64 = ((u64)compbit_base_post_divide *
g->ltc_count) << ltc_ltcs_ltss_cbc_base_alignment_shift_v();
if (compbit_base_post_multiply64 < compbit_store_iova)
compbit_base_post_divide++;
/* Bug 1477079 indicates sw adjustment on the posted divided base. */
if (g->ops.ltc.cbc_fix_config)
compbit_base_post_divide =
g->ops.ltc.cbc_fix_config(g, compbit_base_post_divide);
gk20a_writel(g, ltc_ltcs_ltss_cbc_base_r(),
compbit_base_post_divide);
gk20a_dbg(gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte,
"compbit base.pa: 0x%x,%08x cbc_base:0x%08x\n",
(u32)(compbit_store_iova >> 32),
(u32)(compbit_store_iova & 0xffffffff),
compbit_base_post_divide);
gr->compbit_store.base_hw = compbit_base_post_divide;
g->ops.ltc.cbc_ctrl(g, gk20a_cbc_op_invalidate,
0, max_comptag_lines - 1);
}
#ifdef CONFIG_DEBUG_FS
void gk20a_ltc_sync_debugfs(struct gk20a *g)
{
u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f();
nvgpu_spinlock_acquire(&g->debugfs_lock);
if (g->mm.ltc_enabled != g->mm.ltc_enabled_debug) {
u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r());
if (g->mm.ltc_enabled_debug)
/* bypass disabled (normal caching ops)*/
reg &= ~reg_f;
else
/* bypass enabled (no caching) */
reg |= reg_f;
gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg);
g->mm.ltc_enabled = g->mm.ltc_enabled_debug;
}
nvgpu_spinlock_release(&g->debugfs_lock);
}
#endif

21
drivers/gpu/nvgpu/gk20a/ltc_gk20a.h
View File

@@ -15,27 +15,8 @@
#ifndef LTC_GK20A_H
#define LTC_GK20A_H
struct gpu_ops;
struct gr_gk20a;
struct zbc_entry;
enum gk20a_cbc_op;
struct gk20a;
int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr);
int gk20a_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op,
u32 min, u32 max);
void gk20a_ltc_init_fs_state(struct gk20a *g);
void gk20a_ltc_isr(struct gk20a *g);
int gk20a_determine_L2_size_bytes(struct gk20a *g);
void gk20a_ltc_set_zbc_color_entry(struct gk20a *g,
struct zbc_entry *color_val,
u32 index);
void gk20a_ltc_set_zbc_depth_entry(struct gk20a *g,
struct zbc_entry *depth_val,
u32 index);
void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr);
#ifdef CONFIG_DEBUG_FS
void gk20a_ltc_sync_debugfs(struct gk20a *g);
#endif
int gk20a_ltc_alloc_phys_cbc(struct gk20a *g, size_t compbit_backing_size);
int gk20a_ltc_alloc_virt_cbc(struct gk20a *g, size_t compbit_backing_size);
#endif

18
drivers/gpu/nvgpu/gk20a/mc_gk20a.c
View File

@@ -235,21 +235,3 @@ bool mc_gk20a_is_intr1_pending(struct gk20a *g,
return is_pending;
}
void gk20a_init_mc(struct gpu_ops *gops)
{
gops->mc.intr_enable = mc_gk20a_intr_enable;
gops->mc.intr_unit_config = mc_gk20a_intr_unit_config;
gops->mc.isr_stall = mc_gk20a_isr_stall;
gops->mc.intr_stall = mc_gk20a_intr_stall;
gops->mc.intr_stall_pause = mc_gk20a_intr_stall_pause;
gops->mc.intr_stall_resume = mc_gk20a_intr_stall_resume;
gops->mc.intr_nonstall = mc_gk20a_intr_nonstall;
gops->mc.intr_nonstall_pause = mc_gk20a_intr_nonstall_pause;
gops->mc.intr_nonstall_resume = mc_gk20a_intr_nonstall_resume;
gops->mc.enable = gk20a_mc_enable;
gops->mc.disable = gk20a_mc_disable;
gops->mc.reset = gk20a_mc_reset;
gops->mc.boot_0 = gk20a_mc_boot_0;
gops->mc.is_intr1_pending = mc_gk20a_is_intr1_pending;
}

1
drivers/gpu/nvgpu/gk20a/mc_gk20a.h
View File

@@ -15,7 +15,6 @@
#define MC_GK20A_H
struct gk20a;
void gk20a_init_mc(struct gpu_ops *gops);
void mc_gk20a_intr_enable(struct gk20a *g);
void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable,
bool is_stalling, u32 mask);

24
drivers/gpu/nvgpu/gk20a/mm_gk20a.c
View File

@@ -2545,27 +2545,3 @@ clean_up:
dma_buf_put(dmabuf);
return err;
}
static bool gk20a_mm_is_bar1_supported(struct gk20a *g)
{
return true;
}
void gk20a_init_mm(struct gpu_ops *gops)
{
gops->mm.gmmu_map = gk20a_locked_gmmu_map;
gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap;
gops->mm.vm_bind_channel = gk20a_vm_bind_channel;
gops->mm.fb_flush = gk20a_mm_fb_flush;
gops->mm.l2_invalidate = gk20a_mm_l2_invalidate;
gops->mm.l2_flush = gk20a_mm_l2_flush;
gops->mm.cbc_clean = gk20a_mm_cbc_clean;
gops->mm.get_iova_addr = gk20a_mm_iova_addr;
gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits;
gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels;
gops->mm.init_pdb = gk20a_mm_init_pdb;
gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw;
gops->mm.init_inst_block = gk20a_init_inst_block;
gops->mm.is_bar1_supported = gk20a_mm_is_bar1_supported;
gops->mm.mmu_fault_pending = gk20a_fifo_mmu_fault_pending;
}

2
drivers/gpu/nvgpu/gk20a/mm_gk20a.h
View File

@@ -439,8 +439,6 @@ void pde_range_from_vaddr_range(struct vm_gk20a *vm,
int gk20a_mm_pde_coverage_bit_count(struct vm_gk20a *vm);
u32 gk20a_mm_get_physical_addr_bits(struct gk20a *g);
struct gpu_ops;
void gk20a_init_mm(struct gpu_ops *gops);
const struct gk20a_mmu_level *gk20a_mm_get_mmu_levels(struct gk20a *g,
u32 big_page_size);
void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *mem,

2
drivers/gpu/nvgpu/gk20a/platform_gk20a.h
View File

@@ -243,9 +243,7 @@ static inline struct gk20a_platform *gk20a_get_platform(
return (struct gk20a_platform *)dev_get_drvdata(dev);
}
extern struct gk20a_platform gk20a_generic_platform;
#ifdef CONFIG_TEGRA_GK20A
extern struct gk20a_platform gk20a_tegra_platform;
extern struct gk20a_platform gm20b_tegra_platform;
extern struct gk20a_platform gp10b_tegra_platform;
#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION

90
drivers/gpu/nvgpu/gk20a/platform_gk20a_generic.c
View File

@@ -1,90 +0,0 @@
/*
* drivers/gpu/nvgpu/gk20a/platform_gk20a_generic.c
*
* GK20A Generic Platform Interface
*
* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/clk.h>
#include "platform_gk20a.h"
#include "hal_gk20a.h"
#include "gk20a.h"
/*
* gk20a_generic_get_clocks()
*
* This function finds clocks in tegra platform and populates
* the clock information to gk20a platform data.
*/
static int gk20a_generic_get_clocks(struct device *pdev)
{
struct gk20a_platform *platform = dev_get_drvdata(pdev);
platform->clk[0] = clk_get_sys("tegra_gk20a.0", "PLLG_ref");
platform->clk[1] = clk_get_sys("tegra_gk20a.0", "pwr");
platform->clk[2] = clk_get_sys("tegra_gk20a.0", "emc");
platform->num_clks = 3;
if (IS_ERR(platform->clk[0]) ||
IS_ERR(platform->clk[1]) ||
IS_ERR(platform->clk[2]))
goto err_get_clock;
clk_set_rate(platform->clk[0], UINT_MAX);
clk_set_rate(platform->clk[1], 204000000);
clk_set_rate(platform->clk[2], UINT_MAX);
return 0;
err_get_clock:
if (!IS_ERR_OR_NULL(platform->clk[0]))
clk_put(platform->clk[0]);
if (!IS_ERR_OR_NULL(platform->clk[1]))
clk_put(platform->clk[1]);
if (!IS_ERR_OR_NULL(platform->clk[2]))
clk_put(platform->clk[2]);
platform->clk[0] = NULL;
platform->clk[1] = NULL;
platform->clk[2] = NULL;
return -ENODEV;
}
static int gk20a_generic_probe(struct device *dev)
{
gk20a_generic_get_clocks(dev);
return 0;
}
static int gk20a_generic_late_probe(struct device *dev)
{
return 0;
}
static int gk20a_generic_remove(struct device *dev)
{
return 0;
}
struct gk20a_platform gk20a_generic_platform = {
.probe = gk20a_generic_probe,
.late_probe = gk20a_generic_late_probe,
.remove = gk20a_generic_remove,
.default_big_page_size = SZ_128K,
};

1
drivers/gpu/nvgpu/gk20a/platform_vgpu_tegra.c
View File

@@ -14,7 +14,6 @@
*/
#include "gk20a.h"
#include "hal_gk20a.h"
#include "platform_gk20a.h"
#include "vgpu/clk_vgpu.h"

137
drivers/gpu/nvgpu/gk20a/regops_gk20a.c
View File

@@ -1,7 +1,7 @@
/*
* Tegra GK20A GPU Debugger Driver Register Ops
*
* Copyright (c) 2013-2016, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -729,138 +729,3 @@ bool is_bar0_global_offset_whitelisted_gk20a(struct gk20a *g, u32 offset)
regop_bsearch_range_cmp);
return valid;
}
static const struct regop_offset_range *gk20a_get_global_whitelist_ranges(void)
{
return gk20a_global_whitelist_ranges;
}
static int gk20a_get_global_whitelist_ranges_count(void)
{
return gk20a_global_whitelist_ranges_count;
}
static const struct regop_offset_range *gk20a_get_context_whitelist_ranges(void)
{
return gk20a_context_whitelist_ranges;
}
static int gk20a_get_context_whitelist_ranges_count(void)
{
return gk20a_context_whitelist_ranges_count;
}
static const u32 *gk20a_get_runcontrol_whitelist(void)
{
return gk20a_runcontrol_whitelist;
}
static int gk20a_get_runcontrol_whitelist_count(void)
{
return gk20a_runcontrol_whitelist_count;
}
static const
struct regop_offset_range *gk20a_get_runcontrol_whitelist_ranges(void)
{
return gk20a_runcontrol_whitelist_ranges;
}
static int gk20a_get_runcontrol_whitelist_ranges_count(void)
{
return gk20a_runcontrol_whitelist_ranges_count;
}
static const u32 *gk20a_get_qctl_whitelist(void)
{
return gk20a_qctl_whitelist;
}
static int gk20a_get_qctl_whitelist_count(void)
{
return gk20a_qctl_whitelist_count;
}
static const struct regop_offset_range *gk20a_get_qctl_whitelist_ranges(void)
{
return gk20a_qctl_whitelist_ranges;
}
static int gk20a_get_qctl_whitelist_ranges_count(void)
{
return gk20a_qctl_whitelist_ranges_count;
}
static int gk20a_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
{
/* The following regops are a hack/war to make up for the fact that we
* just scribbled into the ctxsw image w/o really knowing whether
* it was already swapped out in/out once or not, etc.
*/
struct nvgpu_dbg_gpu_reg_op ops[4];
unsigned int i;
for (i = 0; i < ARRAY_SIZE(ops); i++) {
ops[i].op = REGOP(WRITE_32);
ops[i].type = REGOP(TYPE_GR_CTX);
ops[i].status = REGOP(STATUS_SUCCESS);
ops[i].value_hi = 0;
ops[i].and_n_mask_lo = 0;
ops[i].and_n_mask_hi = 0;
}
/* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control_sel1_r();*/
ops[0].offset = 0x00419e08;
ops[0].value_lo = 0x1d;
/* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control5_r(); */
ops[1].offset = 0x00419e58;
ops[1].value_lo = 0x1;
/* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control3_r(); */
ops[2].offset = 0x00419e68;
ops[2].value_lo = 0xaaaa;
/* gr_pri_gpcs_tpcs_sm_dsm_perf_counter4_control_r(); */
ops[3].offset = 0x00419f40;
ops[3].value_lo = 0x18;
return dbg_s->g->ops.dbg_session_ops.exec_reg_ops(dbg_s, ops,
ARRAY_SIZE(ops));
}
void gk20a_init_regops(struct gpu_ops *gops)
{
gops->regops.get_global_whitelist_ranges =
gk20a_get_global_whitelist_ranges;
gops->regops.get_global_whitelist_ranges_count =
gk20a_get_global_whitelist_ranges_count;
gops->regops.get_context_whitelist_ranges =
gk20a_get_context_whitelist_ranges;
gops->regops.get_context_whitelist_ranges_count =
gk20a_get_context_whitelist_ranges_count;
gops->regops.get_runcontrol_whitelist =
gk20a_get_runcontrol_whitelist;
gops->regops.get_runcontrol_whitelist_count =
gk20a_get_runcontrol_whitelist_count;
gops->regops.get_runcontrol_whitelist_ranges =
gk20a_get_runcontrol_whitelist_ranges;
gops->regops.get_runcontrol_whitelist_ranges_count =
gk20a_get_runcontrol_whitelist_ranges_count;
gops->regops.get_qctl_whitelist =
gk20a_get_qctl_whitelist;
gops->regops.get_qctl_whitelist_count =
gk20a_get_qctl_whitelist_count;
gops->regops.get_qctl_whitelist_ranges =
gk20a_get_qctl_whitelist_ranges;
gops->regops.get_qctl_whitelist_ranges_count =
gk20a_get_qctl_whitelist_ranges_count;
gops->regops.apply_smpc_war =
gk20a_apply_smpc_war;
}

3
drivers/gpu/nvgpu/gk20a/regops_gk20a.h
View File

@@ -1,7 +1,7 @@
/*
* Tegra GK20A GPU Debugger Driver Register Ops
*
* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -49,5 +49,4 @@ static inline bool reg_op_is_read(u8 op)
bool is_bar0_global_offset_whitelisted_gk20a(struct gk20a *g, u32 offset);
void gk20a_init_regops(struct gpu_ops *gops);
#endif /* REGOPS_GK20A_H */

58
drivers/gpu/nvgpu/gk20a/therm_gk20a.c
View File

@@ -33,58 +33,6 @@ static int gk20a_init_therm_setup_sw(struct gk20a *g)
return 0;
}
static int gk20a_init_therm_setup_hw(struct gk20a *g)
{
u32 v;
/* program NV_THERM registers */
gk20a_writel(g, therm_use_a_r(), therm_use_a_ext_therm_0_enable_f() |
therm_use_a_ext_therm_1_enable_f() |
therm_use_a_ext_therm_2_enable_f());
/* priority for EXT_THERM_0 event set to highest */
gk20a_writel(g, therm_evt_ext_therm_0_r(),
therm_evt_ext_therm_0_slow_factor_f(0x2) |
therm_evt_ext_therm_0_priority_f(3));
gk20a_writel(g, therm_evt_ext_therm_1_r(),
therm_evt_ext_therm_1_slow_factor_f(0x6) |
therm_evt_ext_therm_1_priority_f(2));
gk20a_writel(g, therm_evt_ext_therm_2_r(),
therm_evt_ext_therm_2_slow_factor_f(0xe) |
therm_evt_ext_therm_2_priority_f(1));
gk20a_writel(g, therm_grad_stepping_table_r(0),
therm_grad_stepping_table_slowdown_factor0_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()) |
therm_grad_stepping_table_slowdown_factor1_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()) |
therm_grad_stepping_table_slowdown_factor2_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()) |
therm_grad_stepping_table_slowdown_factor3_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
therm_grad_stepping_table_slowdown_factor4_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
gk20a_writel(g, therm_grad_stepping_table_r(1),
therm_grad_stepping_table_slowdown_factor0_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
therm_grad_stepping_table_slowdown_factor1_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
therm_grad_stepping_table_slowdown_factor2_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
therm_grad_stepping_table_slowdown_factor3_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
therm_grad_stepping_table_slowdown_factor4_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
v = gk20a_readl(g, therm_clk_timing_r(0));
v |= therm_clk_timing_grad_slowdown_enabled_f();
gk20a_writel(g, therm_clk_timing_r(0), v);
v = gk20a_readl(g, therm_config2_r());
v |= therm_config2_grad_enable_f(1);
v |= therm_config2_slowdown_factor_extended_f(1);
gk20a_writel(g, therm_config2_r(), v);
gk20a_writel(g, therm_grad_stepping1_r(),
therm_grad_stepping1_pdiv_duration_f(32));
v = gk20a_readl(g, therm_grad_stepping0_r());
v |= therm_grad_stepping0_feature_enable_f();
gk20a_writel(g, therm_grad_stepping0_r(), v);
return 0;
}
int gk20a_init_therm_support(struct gk20a *g)
{
u32 err;
@@ -153,9 +101,3 @@ int gk20a_elcg_init_idle_filters(struct gk20a *g)
gk20a_dbg_fn("done");
return 0;
}
void gk20a_init_therm_ops(struct gpu_ops *gops)
{
gops->therm.init_therm_setup_hw = gk20a_init_therm_setup_hw;
gops->therm.elcg_init_idle_filters = gk20a_elcg_init_idle_filters;
}

3
drivers/gpu/nvgpu/gk20a/therm_gk20a.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011 - 2015, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -19,7 +19,6 @@
struct gpu_ops;
struct gk20a;
void gk20a_init_therm_ops(struct gpu_ops *gops);
int gk20a_elcg_init_idle_filters(struct gk20a *g);
int gk20a_init_therm_support(struct gk20a *g);

4
drivers/gpu/nvgpu/gm20b/ltc_gm20b.h
View File

@@ -35,4 +35,8 @@ int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op,
void gm20b_ltc_isr(struct gk20a *g);
u32 gm20b_ltc_cbc_fix_config(struct gk20a *g, int base);
void gm20b_flush_ltc(struct gk20a *g);
int gm20b_ltc_alloc_phys_cbc(struct gk20a *g,
size_t compbit_backing_size);
int gm20b_ltc_alloc_virt_cbc(struct gk20a *g,
size_t compbit_backing_size);
#endif

47
drivers/gpu/nvgpu/vgpu/gk20a/vgpu_gr_gk20a.c
View File

@@ -1,47 +0,0 @@
/*
* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "gk20a/gk20a.h"
#include "vgpu_gr_gk20a.h"
static int vgpu_gk20a_init_fs_state(struct gk20a *g)
{
struct gr_gk20a *gr = &g->gr;
u32 tpc_index, gpc_index;
u32 sm_id = 0;
gk20a_dbg_fn("");
for (tpc_index = 0; tpc_index < gr->max_tpc_per_gpc_count;
tpc_index++) {
for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
if (tpc_index < gr->gpc_tpc_count[gpc_index]) {
g->gr.sm_to_cluster[sm_id].tpc_index =
tpc_index;
g->gr.sm_to_cluster[sm_id].gpc_index =
gpc_index;
sm_id++;
}
}
}
gr->no_of_sm = sm_id;
return 0;
}
void vgpu_gk20a_init_gr_ops(struct gpu_ops *gops)
{
gops->gr.init_fs_state = vgpu_gk20a_init_fs_state;
}

21
drivers/gpu/nvgpu/vgpu/gk20a/vgpu_gr_gk20a.h
View File

@@ -1,21 +0,0 @@
/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __VGPU_GR_GK20A_H__
#define __VGPU_GR_GK20A_H__
#include "gk20a/gk20a.h"
void vgpu_gk20a_init_gr_ops(struct gpu_ops *gops);
#endif

29
drivers/gpu/nvgpu/vgpu/gk20a/vgpu_hal_gk20a.c
View File

@@ -1,29 +0,0 @@
/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "gk20a/hal_gk20a.h"
#include "vgpu/vgpu.h"
#include "vgpu_gr_gk20a.h"
int vgpu_gk20a_init_hal(struct gk20a *g)
{
int err;
err = gk20a_init_hal(g);
if (err)
return err;
vgpu_init_hal_common(g);
vgpu_gk20a_init_gr_ops(&g->ops);
return 0;
}

5
drivers/gpu/nvgpu/vgpu/vgpu.c
View File

@@ -29,7 +29,6 @@
#include "vgpu/vgpu.h"
#include "vgpu/fecs_trace_vgpu.h"
#include "vgpu/clk_vgpu.h"
#include "gk20a/hal_gk20a.h"
#include "gk20a/ctxsw_trace_gk20a.h"
#include "gk20a/tsg_gk20a.h"
#include "gk20a/gk20a_scale.h"
@@ -451,10 +450,6 @@ static int vgpu_init_hal(struct gk20a *g)
int err;
switch (ver) {
case GK20A_GPUID_GK20A:
gk20a_dbg_info("gk20a detected");
err = vgpu_gk20a_init_hal(g);
break;
case GK20A_GPUID_GM20B:
case GK20A_GPUID_GM20B_B:
gk20a_dbg_info("gm20b detected");

1
drivers/gpu/nvgpu/vgpu/vgpu.h
View File

@@ -102,7 +102,6 @@ int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
size_t size_out);
void vgpu_init_hal_common(struct gk20a *g);
int vgpu_gk20a_init_hal(struct gk20a *g);
int vgpu_gm20b_init_hal(struct gk20a *g);
int vgpu_gp10b_init_hal(struct gk20a *g);